Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第15668号 / 工博第3326号 / 新制||工||1502(附属図書館) / 28205 / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 引原 隆士, 教授 木本 恒暢, 教授 和田 修己 / 学位規則第4条第1項該当

This thesis presents a solid state approach to the ion detection system used in the back-end of modern mass spectrometers. Although various techniques already exist to detect ions – even with the sensitivity of a single particle, the existing techniques require high voltage or lower operation temperature to counteract the noise inherent in the system. The suggested design presents an alternative to the more popular detection system whereby the requirement of high operation voltage or low operation temperature can be precluded. This is made possible through the gate capacitance of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). This thesis presents the design that utilizes the MOSFET as an ion signal amplifier; including the simulation and silicon testbench results.

According to non-stopable progress in wireless communications, it is desirable to integrate the RF front-end with the baseband building blocks of communication circuits into a one chip in the recent years. The CMOS technology advances, this is the reason why it becomes attractive for system-on-a-chip implementation, but CMOS device is getting shrink, so the channel electric field increasing and the hot carrier (HCI) effect becomes more significant. If the oxide is scaled down to less than 3 nm, then there is the possibility of soft or hard oxide breakdown (S/HBD) often takes place. As a result of the oxide trapping and interface generation is the long term performance drift and related reliability problems in devices and circuits. During the scaling and increasing chip power dissipation operating temperatures for device have also is increasing. Another reliability concern is the negative bias temperature instability (NBTI) caused by the interface traps under high temperature and negative gate voltage bias are arising while the operation temperature of devices is increasing. Parameter’s extraction is a very important part of the current electronic components modeling process, as it looking for the value of the unknown parameters in mathematical model, which represents physical behavior of given electronic component. The problem of parameter extraction is that fits electronic components mathematical model to a measured data set is an ill-posed problem and its solution is inherently difficult. This diploma thesis presents the parameter extraction, optimization methodology and verifies it on a case study of a MOSFET mathematical models (LEVEL1, LEVEL2 and LEVEL3) parameter extraction. The presented nonlinear method is based on the method of the least squares, which is solved with the aid of Levenberg- Marquardt’s algorithm.

This work deals with methods used in design of low voltage operational amplifiers. It describes some of the most commonly used methods. Properties of these methods are verified by computer simulation of operational transconductance amplifiers that are utilizing them.

This text analyzes characteristics of audio power amplifiers in class D. The emphasis is placed on more detailed analysis of modulators, drivers, connection topology of power transistors. In the next section of text are analyzed available integrated circuits of power amplifiers in class D which are manufactured by world producers. The last part describes design of all parts of amplifier in class D with discrete components and also of power supplies. According to the plans, the individual parts are made. All parts are tested by measurements and results are evaluated.

Les travaux menés pendant cette thèse se concentrent sur l'étude de technologies avancées de MOSFET, plus précisément de FinFET à triple-grille et de nanofils à grille enrobante. Ils ont été fabriqués pour le nœud technologique 10 nm, suivant le même procédé de fabrication à l'exception de la fabrication d'une quatrième grille pour les nanofils. Ces composants sont étudiés en régime statique afin de déterminer les principaux paramètres de leur modèle électrique. Des études à très faible température (< 10 K) et faible tension de drain (< 1 mV) montrent la présence de transport quantique dû aux niveaux d'énergie discrets dans les bandes de conduction et de valence. L'étude du bruit électrique en 1/f montre une bonne maîtrise du procédé d'oxydation de la grille ainsi que le changement de mécanisme de bruit sous l'effet de transport quantique. Différentes spectroscopies de bruit basse fréquence (i.e. étude du bruit de génération-recombinaison en fonction de la température) ont permis d'identifier les pièges contenus dans le film de silicium, donnant ainsi la possibilité d'incriminer les étapes de fabrications les plus critiques. / The work led within this thesis focuses on the study of advanced MOSFET technologies, more precisely of triple-gate FinFETs and Gate-All-Around nanowire FETs. They were fabricated for the 10-nm technological node, following the same recipe except for the build of a fourth gate in nanowire devices.The devices have been studied in static regime in order to determine the main parameters of their electrical model. Low temperature (<10 K) and low drain voltage (1mV) studies highlighted the existence of quantum transport that is due to discrete energy levels within the conduction and valence bands. The study of the 1/f noise testifies the good control of the gate oxidation process and evidences a change in the noise mecanism under quantum transport.Numerous low frequency noise spectroscopies (i.e. study of the generation-recombination noise as a function of the temperature) let us identify silicon film traps, thus giving indication of the critical process steps that are responsible for the generation-recombination noise.

Les travaux réalisés pendant cette thèse se focalisent sur l'étude de transistors double grille UTBOX complètement délpétés fabriqués pour le nœud technologique 16 nm. Les performances de ces composants en courant continu et en fonction de la température ont été évaluées. Les pièges localisés dans le film de silicium ont été identifiés à l’aide de la spectroscopie de bruit basse fréquence, donnant ainsi la possibilité d'évaluer les étapes de fabrications afin de les optimiser. Un pic inhabituel de transconductance a été observé dans les caractéristiques de transfert obtenues à faibles températures (77 K et 10 K). Ce phénomène est plus probablement lié à un effet tunnel à travers des dopants diffusés à partir des extensions de source et drain dans le canal. Le mécanisme de transport quantique relié à la dégénérescence de niveaux d'énergie dans la bande de conduction a été mis en évidence à température cryogéniques et à très faibles polarisations. Une nouvelle approche théorique valide en inversion modérée a été développée pour les modèles de fluctuations de mobilité et de fluctuations de mobilité corrélés aux fluctuations du nombre de porteurs. Les résultats indiquent que le changement du mécanisme de transport des porteurs est accompagné par un changement du mécanisme du bruit en 1/f . / The work done during this thesis focuses on the study of fully depleted double gate UTBOX transistors manufactured for the 16 nm technology node. The performances of these components in DC and as a function of temperature were evaluated. The traps located in the silicon film have been identified using low frequency noise spectroscopy, giving the possibility of evaluating the manufacturing steps in order to optimize them. An unusual peak of transconductance was observed in the transfer characteristics obtained at low temperatures (77 K and 10 K). This phenomenon is most likely related to a tunneling effect through dopants scattered from the source and drain extensions in the channel. The quantum transport mechanism related to the degeneracy of energy levels in the conduction band has been demonstrated at cryogenic temperatures and at very low polarizations. A new theoretical approach valid in moderate inversion has been developed for models of mobility fluctuations and mobility fluctuations correlated with the number of carriers fluctuations. The results indicate that the change in carrier transport mechanism is accompanied by a change in the 1 / f noise mechanism.

This thesis describes an experimental study and modeling of the current-transconductance dependence of the ALD1106, ALD1107, and CD4007 arrays. The study tests the hypothesis that the I-gm dependence of these 7.8 µm to 10 µm MOSFETs conforms to the Advanced Compact Model (ACM). Results from performed measurements, however, do not support this expectation. Despite the relatively large length, both ALD1106 and ALD1107 show sufficiently pronounced ‘short-channel’ effects to render the ACM inadequate. As a byproduct of this effort, we confirmed the modified ACM equation. With an m factor of approximately 0.6, it captures the I-gm dependence with sub-28% maximum error and sub-10% average error. The paper also introduces several formulas and procedures for I-gm model extraction and tuning. These are not specific to the ALD transistor family and can apply to MOSFETs with different physical size and electrical performance.

No description available.

京都大学 / 0048 / 新制・課程博士 / 博士(情報学) / 甲第17992号 / 情博第514号 / 新制||情||91(附属図書館) / 80836 / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 小野寺 秀俊, 教授 佐藤 高史, 教授 松山 隆司 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM