京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第18286号 / 工博第3878号 / 新制||工||1595(附属図書館) / 31144 / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 白石 誠司, 准教授 浅野 卓 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

No description available.

No description available.

Starting from small scale laboratories to the highly sophisticated industrial facilities, monitoring and control forms the most integral part. In order to perform this continuous monitoring we require an interface, that would operate between the system and its processing conditions and in turn which facilitates us to act accordingly. This interface is called as a sensor. There are various types of sensors available which have wide range of functionality in various different fields. The use of transparent conducting oxide (TCO) in the field of sensor applications has increased and has been the subject of extensive research. Good electrical properties, good optical properties, wide band gap, portability, easy processing, and low cost has led to the extensive research on TCO for sensor applications. For this research purpose two specific types of sensor applications namely, light sensing and humidity sensing were considered. For this purpose, two sets of metal-oxide-semiconductor field effect transistors (MOSFET) with one set having transparent aluminum doped zinc oxide and the other having indium tin oxide respectively as their gate metal was fabricated. The MOSFETs were fabricated using a four level mask and tested.

Progress in advanced microlithography and deposition techniques have made feasible high- k dielectric materials for MOS transistors. The continued scaling of CMOS devices is pushing the Si-SiO2 to its limit to consider high-k gate dielectrics. The demand for faster, low power, smaller, less expensive devices with good functionality and higher performance increases the demand for high-k dielectric based MOS devices. This thesis gives an in-depth study of threshold voltages of PMOS and NMOS transistors using various high-k dielectric materials like Tantalum pent oxide (Ta2O5), Hafnium oxide (HfO2), Zirconium oxide (ZrO2) and Aluminum oxide (Al2O3) gate oxides. Higher dielectric constant may lead to high oxide capacitance (Cox), which affects the threshold voltage (VT) of the device. The working potential of MOS devices can be increased by high dielectric gate oxide and work function of gate metal which may also influence the threshold voltage (VT). High dielectric materials have low gate leakage current, high breakdown voltage and are thermally stable on Silicon Substrate (Si). Different kinds of deposition techniques for different gate oxides, gate metals and stability over silicon substrates are analyzed theoretically. The impact of the properties of gate oxides such as oxide thickness, interface trap charges, doping concentration on threshold voltage were simulated, plotted and studied. This study involved comparisons of oxides-oxides, metals-metals, and metals-oxides. Gate metals and alloys with work function of less than 5eV would be suitable candidates for aluminum oxide, hafnium oxide etc. based MOSFETs.

Power management solutions such as voltage regulator (VR) mandate DC-DC converters with high power density, high switching frequency and high efficiency to meet the needs of future computers and telecom equipment. The trend towards DC-DC converters with higher switching frequency presents significant challenges to power MOSFET technology. Optimization of the MOSFETs plays an important role in improving low-voltage DC-DC converter performance. This dissertation focuses on developing and optimizing high performance low voltage power MOSFETs for high frequency applications. With an inherently large gate charge, the trench MOSFET suffers significant switching power losses and cannot continue to provide sufficient performance in high frequency applications. Moreover, the influence of parasitic impedance introduced by device packaging and PCB assembly in board level power supply designs becomes more pronounced as the output voltage continues to decrease and the nominal current continues to increase. This eventually raises the need for highly integrated solutions such as power supply in package (PSiP) or on chip (PSoC). However, it is often more desirable in some PSiP architectures to reverse the source/drain electrodes from electrical and/or thermal point of view. In this dissertation, a stacked-die Power Block PSiP architecture is first introduced to enable DC-DC buck converters with a current rating up to 40 A and a switching frequency in the MHz range. New high- and low-side NexFETs are specially designed and optimized for the new PSiP architecture to maximize its efficiency and power density. In particular, a new NexFET structure with iv its source electrode on the bottom side of the die (source-down) is designed to enable the innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint. It is also observed that in synchronous buck converter very fast switching of power MOSFETs sometimes leads to high voltage oscillations at the phase node of the buck converter, which may introduce additional power loss and cause EMI related problems and undesirable electrical stress to the power MOSFET. At the same time, the synchronous MOSFET plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact the performance of the SyncFET. This dissertation introduces a new approach to effectively overcome the aforementioned challenges associated with the state-of-art technology. The threshold voltage of the low-side NexFET is intentionally reduced to minimize the conduction and body diode related power losses. Meanwhile, a monolithically integrated gate voltage pull-down circuitry is proposed to overcome the possible Cdv/dt induced turn-on issue inadvertently induced by the low VTH SynFET. Through extensive modeling and simulation, all these innovative concepts are integrated together in a power module and fabricated with a 0.35µm process. With all these novel device technology improvements, the new power module delivers a significant improvement in efficiency and offers an excellent solution for future high frequency, high current density DC-DC converters. Megahertz operation of a Power v Block incorporating these new device techniques is demonstrated with an excellent efficiency observed.

Three growing power electronics applications have massive requirements for properly operating their medium-voltage and high-voltage systems: electric transportation, renewable energy, and the power grid. Their needs include dense power systems with higher efficiency and higher voltage and current devices. This requires devices with higher switching frequencies to lower the size of the passives in the converter and devices that can withstand higher operating temperatures as components move closer together to improve power densities. Devices that achieve higher switching speeds and lower specific on-state resistances also reduce losses. Wide bandgap devices (WBG) like silicon carbide (SiC) have a higher bandgap, higher electric field strength, higher thermal conductivity, and lower carrier concentration than silicon (Si). This allows for higher temperature operation, faster switching, higher voltage blocking, and lower power losses, directly meeting the requirements of the previously noted applications. However, the current packaging schemes are limiting the ability of SiC to operate in these applications by applying packaging schemes used for Si. Therefore, it is critical to use and refine advanced packaging techniques so that WBG devices can better operate and meet the growing demands of these power electronic applications. Low-inductance, wirebond-less, high-density, scalable modules are possible due to advanced packaging methods. While beneficial to the operation and design, these techniques introduce new challenges to the fabrication process. This requires refinement to improve the yield of sandwich-structure modules with wirebond-less interconnects. For this module, encapsulated, silver-sintered substrates reduce the peak electric field within the package, improving the partial discharge inception voltage to meet insulation requirements. It is essential to have a uniform bondline between the substrates to achieve all bond connections and improve reliability. Silver sintering is also used to attach the molybdenum (Mo) post interconnects. These interconnects allow for sandwich-structure modules with low inductances; however, they have tolerance variation from manufacturing and bondline thicknesses, which become problematic for multi-chip power modules with an increased number of die and posts. The variation results in tilt, causing some posts to disconnect altogether. Additionally, soldering MCPMs involves a large thermal mass that the soldering reflow profile from a datasheet does not account for. Ultimately, these fabrication concerns can result in misalignment or disconnected post interconnects to the top substrate. Post interconnect planarity and alignment are vital for this multi-chip power module to avoid open or shorted connections that can derate switch positions. This thesis aims to refine each packaging step in assembling a wirebond-less, multi-chip power module. The bond uniformity of silver (Ag) sintering is addressed in dried preform and wet paste cases. The soldering methods are explored and improved by creating a modified reflow profile for large thermal masses and introducing pressure to reduce bondline variation and voiding content. The entire sandwich structure module is analyzed in a statistical tolerance analysis to understand which component introduces the most variation and height mismatch, providing insight as to which packaging techniques need further control to improve the yield of multi-chip power modules. / Master of Science / The electrification of many systems worldwide has increased the need for compact, efficient power electronics. Their applications span electric transportation, renewable energy systems, grid applications, and data centers, to name a few medium-voltage applications. Wide bandgap (WBG) semiconductors can outperform silicon in these applications, offering higher temperature robustness, higher efficiency performance, and higher voltage capabilities. The faster switching will reduce the size and weight of the converters containing these devices. However, using typical packaging schemes such as wirebonds will limit the potential of WBG devices in these applications. Advanced packaging techniques have been developed to increase the electric field strength, reduce the power loop inductances, reduce electromagnetic interference from fast-switching transients, and improve the power densities of multi-chip power modules for medium voltage and current applications. However, these packaging techniques are not trivial to implement and have resulted in a low yield of these modules. This thesis aims to refine each packaging step in assembling a wirebond-less, multi-chip power module. The bond uniformity of silver sintering is addressed in cases of dried preform and wet paste. The soldering methods are explored and improved by creating a modified reflow profile for large thermal masses and introducing pressure to reduce bondline variation and voiding content. The entire sandwich structure module is analyzed in a statistical tolerance analysis to understand which component introduces the most variation and height mismatch, providing insight as to which packaging techniques need further control to improve the yield of multi-chip power modules.

The automotive sector finds itself undergoing a significant and substantial transformation, propelled by the pronounced proliferation of electric vehicles (EVs) and autonomous driving technologies. As the industry proactively adapts to embrace this, an increasingly pressing demand becomes evident for higher performance, reliability, sustainability, and speed. Semiconductor packages emerge as primary catalysts within this ongoing revolution, positioned squarely at the forefront to assume a critical and indispensable function in facilitating the realization of these fundamental objectives. Commercial vehicle manufacturers are taking steps to respond to these demands for sustainability and speed, the driving force in facilitating this being the shift from Si IGBTs to SiC MOSFETs. Silicon Carbide is an increasingly popular choice in inverter module fabrication for electric vehicle applications owing to its inherent characteristics such as reduced on resistance, higher blocking voltage, and higher temperature stability that enable high power density, increased efficiency, and speeds. This work focuses on developing and fabricating a high-density 1.7 kV, 300 A SiC MOSFET half-bridge power module tailored for a 280-320 kW, 2-level inverter configuration. Co-designed with the busbar and gate driver, the custom power module stresses efficient heat dissipation, minimized parasitic inductance, and a compact footprint. Key target parameters to achieve optimal performance include a Rdson below 20 mΩ, Rthjc under 0.2 K/W and a switching time below 20 ns. The proposed module features a double-sided cooling sandwiched structure, an integrated thermistor for health and degradation monitoring, and incorporates three Wolfspeed 3rd generation 1.7 kV, 18 mΩ devices per switch position. The simulated power loop inductance is 14.5 nH, the simulated parasitic resistance is 0.265 m, and the simulated junction-to-case thermal resistance is 0.12182 ℃/W. To keep the die temperature below 150 ℃, a cooling coefficient of 5500 W/m2 is necessary. / Master of Science / The automotive sector is in the midst of a major transformation, propelled by the noticeable spread of electric vehicles (EVs) and autonomous driving technologies. As the industry actively evolves to accommodate this, an increasingly pressing demand becomes apparent for higher performance, reliability, sustainability, and speed. Semiconductor packages are at the forefront of this transformation, playing a crucial role in achieving these goals. Commercial vehicle makers are taking steps to respond to these demands for sustainability and speed, the driving force for this being the shift from Si IGBTs to SiC MOSFETs. Silicon Carbide is an increasingly popular choice in inverter module fabrication for electric vehicle applications owing to its inherent characteristics such as reduced resistance, higher blocking voltage, and higher temperature stability that enable high power density, increased efficiency, and speeds. This study focuses on creating a compact and efficient power module for commercial electric vehicle applications. The designed module is capable of handling high power levels while remaining compact, thus prioritizing power density. This is carefully designed to ensure it cools down effectively, minimizes unnecessary energy losses, and has a small footprint. Certain key features, such as its commutation speed, current carrying capacity, and thermal and mechanical limitations, were also studied. A temperature sensor was incorporated to monitor its health and performance over time. Simulations were performed to validate that this module performs well in terms of its resistances in the electrical conduction path and the oath of heat dissipation.

The scaling of semiconductor transistors has led to a decrease in thickness of the silicon dioxide layer used as gate dielectric. The thickness of the silicon dioxide layer is reduced to increase the gate capacitance, thus increasing the drain current. If the thickness of the gate dielectric decreases below 2nm, the leakage current due to the tunneling increases drastically. Hence it is necessary to replace the gate dielectric, silicon dioxide, with a physically thicker oxide layer of high-k materials like Hafnium oxide and Titanium oxide. High-k dielectric materials allow the capacitance to increase without a huge leakage current. Hafnium oxide and Titanium oxide films are deposited by reactive magnetron sputtering from Hafnium and Titanium targets respectively. These oxide layers are used to create metal-insulator-metal (MIM) structures using aluminum as the top and bottom electrodes. The films are deposited at various O2/Ar gas flow ratios, substrate temperatures, and process pressures. After attaining an exact recipe for these oxide layers that exhibit the desired parameters, MOS capacitors are fabricated with n-Si and p-Si substrates having aluminum electrodes at the top and bottom of each. Comparing the parameters of Hafnium oxide- and Titanium oxide- based MOS capacitors, MOSFET devices are designed with Hafnium oxide as gate dielectric.

No description available.