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This dissertation introduces a hierarchical optimization framework for power converter-based energy management systems, with a primary focus on weight minimization. Emphasizing modularity and scalability, the research systematically tackles the challenges in optimizing these systems, addressing complex design variables, couplings, and the integration of heterogeneous models. The study begins with a comparative evaluation of various metaheuristic optimization methods applied to power inductors and converters, including genetic algorithm, particle swarm optimization, and simulated annealing. This is complemented by a global sensitivity analysis using the Morris method to understand the impact of different design variables on the design objectives and constraints in power electronics. Additionally, a thorough evaluation of different modeling methods for key components is conducted, leading to the validation of selected analytical models at the component level through extensive experiments. Further, the research progresses to studies at the converter level, focusing on a weight-optimized design for the thermal management systems for silicon carbide (SiC) MOSFET-based modular converters and the development of a hierarchical digital control system. This stage includes a thorough assessment of the accuracy of small-signal models for modular converters. At this point, the research methodically examines various design constraints, notably thermal considerations and transient responses. This examination is critical in understanding and addressing the specific challenges associated with converter-level design and the implications on system performance. The dissertation then presents a systematic approach where design variables and constraints are intricately managed across different hierarchies. This strategy facilitates the decoupling of subsystem designs within the same hierarchy, simplifying future enhancements to the optimization process. For example, component databases can be expanded effortlessly, and diverse topologies for converters and subsystems can be incorporated without the need to reconfigure the optimization framework. Another notable aspect of this research is the exploration of the scalability of the optimization architecture, demonstrated through design examples. This scalability is pivotal to the framework's effectiveness, enabling it to adapt and evolve alongside technological advancements and changing design requirements. Furthermore, this dissertation delves into the data transmission architecture within the hierarchical optimization framework. This architecture is not only critical for identifying optimal performance measures, but also for conveying detailed design information across all hierarchy levels, from individual components to entire systems. The interrelation between design specifications, constraints, and performance measures is illustrated through practical design examples, showcasing the framework's comprehensive approach. In summary, this dissertation contributes a novel, modular, and scalable hierarchical optimization architecture for the design of power converter-based energy management systems. It offers a comprehensive approach to managing complex design variables and constraints, paving the way for more efficient, adaptable, and cost-effective power system designs. / Doctor of Philosophy / This dissertation introduces an innovative approach to designing energy control systems, inspired by the creativity and adaptability of a Lego game. Central to this concept is a layered design methodology. The journey begins with power components, the fundamental 'Lego bricks'. Each piece is meticulously optimized for compactness, forming the robust foundation of the system. Like connecting individual Lego bricks into a module, these power components come together to form standardized power converters. These converters offer flexibility and scalability, similar to how numerous structures can be built from the same set of Lego pieces. The final layer involves assembling these power converters in order to construct comprehensive energy control systems. This mirrors the process of using Lego subassemblies to build larger, more intricate structures. At this system-level design, the standardized converters are integrated to optimize overall system performance. Key to this dissertation's methodology is an emphasis on modularity and scalability. It enables the creation of diverse energy control systems of varying sizes and functionalities from these fundamental units. The research delves into the intricacies of design variables and constraints, ensuring that each 'Lego piece' contributes optimally to the bigger picture. This includes exploring the scalability of the architecture, allowing it to evolve with technological advancements and design requirements, as well as examining data transmission within the system to ensure efficient data communication across all levels. In essence, this dissertation is about recognizing the potential in the smallest components and understanding their role in the grand scheme of the system. It is akin to playing a masterful game of Lego, where building something greater from small, well-designed parts leads to more efficient, adaptable, and cost-effective energy control system designs. This approach is particularly relevant for applications in transportation systems and renewable energy in remote locations, showcasing the universal applicability of this 'Lego game' to energy management.

Microinverter has become a new trend for photovoltaic (PV) grid-tie systems due to its advantages which include greater energy harvest, simplified system installation, enhanced safety, and flexible expansion. Since an individual microinverter system is typically attached to the back of a PV module, it is desirable that it has a long lifespan that can match PV modules, which routinely warrant 25 years of operation. In order to increase the life expectancy and improve the long-term reliability, electrolytic capacitors must be avoided in microinverters because they have been identified as an unreliable component. One solution to avoid electrolytic capacitors in microinverters is using a two-stage architecture, where the high voltage direct current (DC) bus can work as a double line ripple buffer. For two-stage electrolyte-free microinverters, a high boost ratio dc-dc converter is required to increase the low PV module voltage to a high DC bus voltage required to run the inverter at the second stage. New high boost ratio dc-dc converter topologies using the hybrid transformer concept are presented in this dissertation. The proposed converters have improved magnetic and device utilization. Combine these features with the converter's reduced switching losses which results in a low cost, simple structure system with high efficiency. Using the California Energy Commission (CEC) efficiency standards a 250 W prototype was tested achieving an overall system efficiency of 97.3%. The power inversion stage of electrolyte-free microinverters requires a high efficiency grid-tie inverter. A transformerless inverter topology with low electro-magnetic interference (EMI) and leakage current is presented. It has the ability to use modern superjunction MOSFETs in conjunction with zero-reverse-recovery silicon carbide (SiC) diodes to achieve ultrahigh efficiency. The performance of the topology was experimentally verified with a tested CEC efficiency of 98.6%. Due to the relatively low energy density of film capacitors compared to electrolytic counterparts, less capacitance is used on the DC bus in order to lower the cost and reduce the volume of electrolyte-free microinverters. The reduced capacitance leads to high double line ripple voltage oscillation on DC bus. If the double line oscillation propagates back into the PV module, the maximum power point tracking (MPPT) performance would be compromised. A control method which prevents the double line oscillation from going to the PV modules, thus improving the MPPT performance was proposed. Finally, a control technique using a single microcontroller with low sampling frequency was presented to effectively eliminate electrolyte capacitors in two-stage microinverters without any added penalties. The effectiveness of this control technique was validated both by simulation and experimental results. / Ph. D.

Due to the limitations of silicon (Si), there is a paradigm shift in research focusing on wide-bandgap-based (WBG) materials. SiC power semiconductors exhibit superiority in terms of switching speed, higher breakdown electric field, and high working temperature, slowly becoming a global solution in harsh medium-voltage (MV) high-power environments. However, to utilize the SiC MOSFET device to achieve those next-generation, high-density, high-efficiency power electronics converters, one must solve a plethora of challenges. For the MV SiC MOSFET device, a high-performance gate-driver (GD) is a key component required to maximize the beneficial SiC MOSFET characteristics. GD units must overcome associated challenges of electro-magnetic interference (EMI) with regards to common-mode (CM) currents and cross-talk, low driving loop inductance required for fast switching, and device short-circuit (SC) protection. Developed GDs (for 1.2 kV, and 10 kV devices) are able to sustain dv/dt higher than 100 V/ns, have less than 5 nH gate loop inductance, and SC protection, turning off the device within 1.5 us. Even with the introduction of SiC MOSFETs, power devices remain the most reliability-critical component in the converter, due to large junction temperature (Tj) fluctuations causing accelerated wear-out. Real-time (online) measurement of the Tj can help improve long-term reliability by enabling active thermal control, monitoring, and prognostics. An online Tj estimation is accomplished by generating integrated intelligence on the GD level. The developed Tj sensor exhibits a maximum error less than 5 degrees Celsius, having excellent repeatability of 1.2 degrees Celsius. Additionally, degradation monitoring and an aging compensation scheme are discussed, in order to maintain the accuracy of the sensor throughout the device's lifetime. Since ultra high-voltage SiC MOSFET devices (20 kV) are impractical, the modular multilevel converter (MMC) emerged as a prospective topology to achieve MV power conversion. If the kernal part of the power-cell (main constitutive part of the MMC converter) is an SiC MOSFET, the design is able to achieve very high-density and high-efficiency. To ensure a successful operation of the power-cell, a systematic design and assessment methodology (DAM) is explored, based on the 10 kV SiC MOSFET power-cell. It simultaneously addresses challenges of high-voltage insulation, high dv/dt and EMI, component and system protections, as well as thermal management. The developed power-cell achieved high-power density of 11.9 kW/l, with measured peak efficiency of n=99.3 %@10 kHz. It successfully operated at Vdc=6 kV, I=84 A, fsw>5 kHz, Tj<150 degrees Celsius and had high switching speeds over 100 V/ns. Lastly, to achieve high-power density and high-efficiency on the MV converter level, challenges of high-voltage insulation, high-bandwidth control, EMI, and thermal management must be solved. Novel switching cycle control (SCC) and integrated capacitor blocked-transistor (ICBT) control methodologies were developed, overcoming the drawbacks of conventional MMC control. These novel types of control enable extreme reduction in passive component size, increase the efficiency, and can operate in dc/dc, dc/ac, mode, potentially opening the modular converter to applications in which it was not previously used. In order to explore the aforementioned benefits, a modular, scalable, 2-cell per arm, prototype MV converter based on the developed power-cell is constructed. The converter successfully operated at Vdc=12 kV, I=28 A, fsw=10 kHz, with high switching speeds, exhibiting high transient immunity in both SCC and ICBT. / Doctor of Philosophy / In medium-voltage applications, such as an electric grid interface in highly populated areas, a ship dc system, a motor drive, renewable energy, etc., land and space can be very limited and expensive. This requires the attributes of high-density, high-efficiency, and reliable distribution by a power electronics converter, whose central piece is the semiconductor device. With the recent breakthrough of SiC devices, these characteristics are obtainable, due to SiC inherent superiority over conventional Si devices. However, to achieve them, several challenges must be overcome and are tackled by this dissertation. Firstly, as a key component required to maximize the beneficial SiC MOSFET characteristics, it is of utmost importance that the high-performance gate-driver be immune to interference issues caused by fast switching and be able to protect the device against a short-circuit, thus increasing the reliability of the system. Secondly, to prevent accelerated degradation of the semiconductor devices due to high-temperature fluctuations, real-time (online) measurement of the Tj is developed on the gate-driver to help improve long-term reliability. Thirdly, to achieve medium-voltage high-power density, high-efficiency modular power conversion, a converter block (power-cell) is developed that simultaneously addresses the challenges of high-voltage insulation, high interference, component and system protections, and thermal management. Lastly, a full-scale medium-voltage modular converter is developed, exploiting the advantages of the fast commutation speed and high switching frequency offered by SiC, meanwhile exhibiting exceptional power density and efficiency.

The electric power system is undergoing a paradigm change on how electric energy is generated, transmitted, and delivered. Power electronics systems which can provide medium-voltage (MV) to high-voltage (HV) output (>13.8 kV ac, > 20 kV dc) with much faster dynamic response (> 10 kHz bandwidth) or high switching-frequency will enable new electronic energy network architectures, like MVDC power delivery, underground solid-state power substation (SSPS), and high-density power electronics building block (PEBB); help drive the levelized cost of electricity (LCOE) of renewable energy on par with conventional power generation; deliver precise and clean power to loads like high-speed electric motors; push the future power system toward 100% renewable energy and energy storage supplied. In the MV to HV area, the power conversion solution is dominated by silicon devices, like SCR, IGCT, and IGBT, which are slow in nature, posing significant switching losses and bulky auxiliary components like turn-on snubbers. Devices in series are required to reach higher voltage. High-frequency HV converter in two-level or three-level bridges running 20 kHz or higher in many emerging applications, like MVDC networks with high-frequency transformers and energy storage integration is hard to be built by silicon solutions. The emerging HV wide-bandgap (WBG) power semiconductors, e.g., 10 kV SiC MOSFETs offer higher blocking capability, faster and more efficient switching performances. This makes the high-frequency power conversion technology feasible for the MV area. To build a MV high-frequency power converter with high-power density, 10 kV SiC MOSFETs in series are required to reach >10 kV operation dc voltage as the single device rating is still limited by the semiconductor process and packaging capability. However, the knowledge of dynamic voltage sharing of high-speed HV SiC devices under high dv/dt rate and effective balancing methods are not fully explored. Both the voltage imbalance and the robust device voltage balancing control are not studied clearly in the existing literature. This dissertation evaluates the voltage imbalance of series-connected 10 kV SiC MOSFETs thoroughly. The parasitic capacitors connected with device terminals are found to be a unique factor for the voltage imbalance of series-connected SiC MOSFETs, which have a significant impact on the dv/dt of different devices based on the detailed analysis. The unbalanced dv/dt and the gate signal mismatch together result in the voltage imbalance of series-connected SiC MOSFETs and a set of new voltage balancing control methods are proposed. Passive capacitor compensation and closed-loop short pulse gate signal control are proposed to solve the voltage imbalance caused by the unbalanced dv/dt. Closed-loop gate delay time control is proposed to solve the voltage imbalance caused by the gate signal mismatch. Two gate driver prototypes are designed and verified for the proposed voltage balancing control methods. As the number of devices increases, the voltage balancing methods under the device-level will be complex and risky to coordinate. Therefore, the converter-level device voltage balancing methods are desired when over three devices are in stack. Therefore, this dissertation proposes to use the 3-level (3L) neutral-point-clamped (NPC) converter structure as a converter-level approach to simplify the voltage balancing control of series-connected SiC MOSFETs. A new modulation strategy is proposed to control the loss of clamping diodes, so compact MV SiC Schottky diodes can be selected to reduce the impact of extra components on the power density. Compared to the phase-leg with direct series-connected SiC MOSFETs, the phase-leg designed with the converter-level approach achieves similar power density, easier voltage balancing control, and better efficiency, which is attractive for both two and four devices in series connection. Finally, this dissertation studies the impact of series-connected 10 kV SiC MOSFETs on MV phase-leg volume reduction with the example of multi-level flying capacitor (FC) converters. The relation between the capacitances of FCs and the device voltage is studied and a new design procedure for FCs is developed to achieve minimum FC energy and regulate the maximum device voltage. With the design procedure, the total FC volumes of a 22 kV 5-level FC converter and a 22 kV 3-level FC converter with series-connected 10 kV SiC MOSFETs are calculated and compared. Series-connected 10 kV SiC MOSFETs are found to help significantly reduce the total FC volume (> 85 %). In summary, this dissertation demonstrates that the direct series connection of 10 kV SiC MOSFETs is a reliable solution for the MV converter design, and the converter-level approach is a better voltage balancing control method. This dissertation also presents a quantitative analysis of the volume reduction enabled by the series-connected 10 kV SiC MOSFETs in MV converter phase-leg design. / Doctor of Philosophy / Emerging industrial applications require medium voltage (MV) power converters. For existing MV converter solutions with Si IGBT, complex system structures are usually required, which affects the efficiency, power density, and cost of the system. For the design of MV converter, the recent 10 kV SiC MOSFET has the promising potential to improve efficiency and power density by adopting a simpler topology and fewer conversion stages. New design challenges also emerge with the new 10 kV SiC MOSFETs and one of them is the device voltage control during the operation. This dissertation mainly focuses on the voltage balancing control of series-connected 10 SiC MOSFETs, which is an attractive solution to build the MV converter phase-leg in a simple structure. Several voltage balance control methods are proposed and compared in this dissertation, which helps justify that the series-connected SiC MOSFET is a reliable approach for the MV converter design. In addition, this dissertation also analyzes the volume reduction enabled by the series-connected SiC MOSFETs with the example of a multi-level flying capacitor converter in dc-ac applications.

Due to the superior characteristics compared to its silicon (Si) counterpart, the wide bandgap (WBG) semiconductor enables next-generation power electronics systems with higher efficiency and higher power density. With higher blocking voltage available, WBG devices, especially the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), have been widely explored in various medium-voltage (MV) applications in both industry and academia. However, due to the high di/dt and high dv/dt during the switching transient, potential overcurrent, overvoltage, and gate failure can greatly reduce the reliability of implementing SiC MOSFETs in an MV system. By utilizing the parasitic inductance between the Kelvin- and the power-source terminal, a short-circuit (SC) and overload (OL) dual-protection scheme is proposed for overcurrent protection. A full design procedure and reliability analysis are given for SC circuit design. A novel OL circuit is proposed to protect OL faults at the gate-driver level. The protection procedure can detect an SC fault within 50 nanoseconds and protect the device within 1.1 microsecond. The proposed method is a simple and effective solution for the potential overcurrent problem of the SiC MOSFET. For SiC MOSFETs in series-connection, the unbalanced voltages can result in system failure due to device breakdown or unbalanced thermal stresses. By injecting current during the turn-off transient, an active dv/dt control method is used for voltage balancing. A 6 kV phase-leg using eight 1.7 kV SiC MOSFETs in series-connection has been tested with voltage balanced accurately. Modeling of the stacked SiC MOSFET with active dv/dt control is also done to summarize the design methodology for an effective and stable system. This method provides a low-loss and compact solution for overvoltage problems when MV SiC MOSFETs are connected in series. Furthermore, a scalable auxiliary power network is proposed to prevent gate failure caused by unstable gate voltage or EMI interference. The two-stage auxiliary power network (APN) architecture includes a wireless power transfer (WPT) converter supplied by a grounded low voltage dc bus, a high step-down-ratio (HSD) converter powered from dc-link capacitors, and a battery-based mini-UPS backup power supply. The auxiliary-power-only pre-charge and discharge circuits are also designed for a 6 kV power electronics building block (PEBB). The proposed architecture provides a general solution of a scalable and reliable auxiliary power network for the SiC-MOSFET-based MV converter. For the WPT converter, a multi-objective optimization on efficiency, EMI mitigation, and high voltage insulation capability have been proposed. Specifically, a series-series-CL topology is proposed for the WPT converter. With the optimization and new topology, a 120 W, 48 V to 48 V WPT converter has been tested to be a reliable part of the auxiliary power network. For the HSD converter, a novel unidirectional voltage-balancing circuit is proposed and connected in an interleaved manner, which provides a fully modular and scalable solution. A ``linear regulator + buck" solution is proposed to be an integrated on-board auxiliary power supply. A 6 kV to 45 V, 100 W converter prototype is built and tested to be another critical part of the auxiliary power network. / Doctor of Philosophy / The wide bandgap semiconductor enables next-generation power electronics systems with higher efficiency and higher power density which will reduce the space, weight, and cost for power supply and conversion systems, especially for renewable energy. However, by pushing the system voltage level higher to medium-voltage of tens of kilovolts, although the system has higher efficiency and simpler control, the reliability drops. This dissertation, therefore, focusing on solving the possible overcurrent, overvoltage, and gate failure issues of the power electronics system that is caused by the high voltage and high electromagnetic interference environment. By utilizing the inductance of the device, a dual-protection method is proposed to prevent the overcurrent problem. The overcurrent fault can be detected within tens of nanoseconds so that the device will not be destroyed because of the huge fault current. When multiple devices are connected in series to hold higher voltage, the voltage sharing between different devices becomes another issue. The proposed modeling and control method for series-connected devices can balance the shared voltage, and make the control system stable so that no overvoltage problem will happen due to the non-evenly distributed voltages. Besides the possible overcurrent and overvoltage problems, losing control of the devices due to the unreliable auxiliary power supply is another issue. This dissertation proposed a scalable auxiliary power network with high efficiency, high immunity to electromagnetic interference, and high reliability. In this network, a wireless power transfer converter is designed to provide enough insulation and isolation capability, while a switched capacitor converter is designed to transfer voltage from several kilovolts to tens of volts. With the proposed overcurrent protection method, voltage sharing control, and reliable auxiliary power network, systems utilizing medium-voltage wide-bandgap semiconductor will have higher reliability to be implemented for different applications.

As power conversion technology is being integrated further into high-reliability environments such as aerospace and electric vehicle applications, a full analysis and understanding of the system's robustness under operating conditions inside and outside the safe-operating-area is necessary. The robustness of power semiconductor devices, a primary component of power converters, has been traditionally evaluated through qualification tests that were developed for legacy silicon (Si) technologies. However, new devices have been commercialized using wide bandgap (WBG) semiconductors including silicon carbide (SiC) and gallium nitride (GaN). These new devices promise enhanced capabilities (e.g., higher switching speed, smaller die size, lower junction capacitances, and higher thermal conductance) over legacy Si devices, thus making the traditional qualification experiments ineffective. This work begins by introducing a new methodology for evaluating the switching robustness of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). Recent static acceleration tests have revealed that SiC MOSFETs can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc-bias higher than the device rated voltage. Under these conditions, SiC MOSFETs show degradation in merely tens of hours at 25si{textdegree}C and tens of minutes at 100si{textdegree}C. Two independent degradation and failure mechanisms are unveiled, one present in the gate-oxide and the other in the bulk-semiconductor regions, detected by the increase in gate leakage current and drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. The GaN high-electron-mobility transistor (HEMT) is a newer WBG device that is being increasingly adopted at an unprecedented rate. Different from SiC MOSFETs, GaN HEMTs have no avalanche capability and withstand the surge energy through capacitive charging, which often causes significant voltage overshoot up to their catastrophic limit. As a result, the dynamic breakdown voltage (BV) and transient overvoltage margin of GaN devices must be studied to fully evaluate the switching ruggedness of devices. This work characterizes the transient overvoltage capability and failure mechanisms of GaN HEMTs under hard-switched turn-off conditions at increasing temperatures, by using a clamped inductive switching circuit with a variable parasitic inductance. This test method allows flexible control over both the magnitude and the dV/dt of the transient overvoltage. The overvoltage robustness of two commercial enhancement-mode (E-mode) p-gate HEMTs was extensively studied: a hybrid drain gate injection transistor (HD-GIT) with an Ohmic-type gate and a Schottky p-Gate HEMT (SP-HEMT). The overvoltage failure of the two devices was found to be determined by the overvoltage magnitude rather than the dV/dt. The HD-GIT and the SP-HEMT were found to fail at a voltage overshoot magnitude that is higher than the breakdown voltage in the static current-voltage measurement. These single event failure tests were repeated at increasing temperatures (100si{textdegree}C and 150si{textdegree}C), and the failures of both devices were consistent with room temperature results. The two types of devices show different failure behaviors, and the underlying mechanisms (electron trapping) have been revealed by physics-based device simulations. Once this single-event overvoltage failure was established, the device's robustness under repetitive overvoltage and surge-energy events remained unclear; therefore, the switching robustness was evaluated for both the HD-GIT and SP-HEMT in a clamped, inductive switching circuit with a 400 V dc bias. A parasitic inductance was used to generate the overvoltage stress events with different overvoltage magnitude up to 95% of the device's destructive limit, different switching periods from 10 ms to 0.33 ms, different temperatures up to 150si{textdegree}C, and different negative gate biases. The electrical parameters of these devices were measured before and after 1 million stress cycles under varying conditions. The HD-GITs showed no failure or permanent degradation after 1-million overvoltage events at different switching periods, or elevated temperatures. The SP-HEMTs showed more pronounced parametric shifts after the 1 million cycles in the threshold voltage, on-resistance, and saturation drain current. Different shifts were also observed from stresses under different overvoltage magnitudes and are attributable to the trapping of the holes produced in impact ionization. All shifts were found to be recoverable after a relaxation period. Overall, the results from these switching-oriented robustness tests have shown that SiC MOSFETs show a tremendous lifetime under static dc-bias experiments, but when excited by hard-switching turn-off events, the failure mechanisms are accelerated. These results suggest the insufficient robustness of SiC MOSFETs under high bias, hard switching conditions, and the significance of using switching-based tests to evaluate the device robustness. These inspired the GaN-based hard-switching turn-off robustness experiments, which further demonstrated the dynamic breakdown voltage phenomena. Ultimately these results suggest that the breakdown voltage and overvoltage margin of GaN HEMTs in practical power switching can be significantly underestimated using the static breakdown voltage. Both sets of experiments provide further evidence for the need for switching-oriented robustness experiments to be implemented by both device vendors and users, to fully qualify and evaluate new power semiconductor transistors. / Doctor of Philosophy / Power conversion technology is being integrated into industrial and commercial applications with the increased use of laptops, server centers, electric vehicles, and solar and wind energy generation. Each of these converters requires the power semiconductor devices to convert energy reliably and safely. textcolor{black}{Silicon has been the primary material for these devices; however,} new devices have been commercialized from both silicon carbide (SiC) and gallium nitride (GaN) materials. Although these devices are required to undergo qualification testing, the standards were developed for silicon technology. The performance of these new devices offers many additional benefits such as physically smaller dimensions, greater power conversion efficiency, and higher thermal operating capabilities. To facilitate the increased integration of these devices into industrial applications, greater robustness and reliability analyses are required to supplement the traditional tests. The work presented here provides two new experimental methodologies to test the robustness of both SiC and GaN power transistors. These methodologies are oriented around hard-switching environments where both high voltage biases and high conduction current exist and stress the intrinsic semiconductor properties. Experimental evaluations were conducted of both material technologies where the electrical properties were monitored over time to identify any degradation effects. Additional analyses were conducted to determine the physics-oriented failure mechanisms. This work provides insight into the limitations of these semiconductor devices for both device designers and manufacturers as well as power electronic system designers.

This thesis provides insight into state-of-the-art 1.2 kV silicon carbide (SiC) power semiconductor transistors, including the MOSFET, BJT, SJT, and normally-on and normally-off JFETs. Both commercial and sample devices from the semiconductor industry's well-known manufacturers were evaluated in this study. These manufacturers include: Cree Inc., ROHM Semiconductor, General Electric, Fairchild Semiconductor, GeneSiC Semiconductor, Infineon Technologies, and SemiSouth Laboratories. To carry out this work, static characterization of each device was performed from 25 ºC to 200 ºC. Dynamic characterization was also conducted through double-pulse tests. Accordingly, this thesis describes the experimental setup used and the different measurements conducted, which comprise: threshold voltage, transconductance, current gain, specific on-resistance, parasitic capacitances, internal gate resistance, and the turn on and turn off switching times and energies. For the latter, the driving method used for each device is described in detail. Furthermore, for the devices that require on-state dc currents, driving losses are taken into consideration. While all of the SiC transistors characterized in this thesis demonstrated low specific on-resistances, the SiC BJT showed the lowest, with Fairchild's FSICBH057A120 SiC BJT having 3.6 mΩ•cm2 (using die area) at 25 ºC. However, the on-resistance of GE's SiC MOSFET proved to have the smallest temperature dependency, increasing by only 59 % from 25 ºC to 200 ºC. From the dynamic characterization, it was shown that Cree's C2M0080120D second generation SiC MOSFET achieved dv/dt rates of 57 V/ns. The SiC MOSFETs also featured low turn off switching energy losses, which were typically less than 70 µJ at 600 V bus voltage and 20 A load current. / Master of Science