In this theses techniques for high-speed digital delta-sigma modulator(DDSM) structures are considered. Four techniques are applied andevaluated: unfolding, increasing the number of delay elements in theinner loop, pipelining/retiming, and optimizations provided by thesynthesis tool. Of interest is to see the speed-area-power trade-offs.For implementation, three different modulators meeting the samerequirements are implemented. Each modulator has a 16-bit input andresults in a 3-bit output. The baseline case is a second-ordermodulator, which has one delay element in its inner loop. Throughoptimization, two new structures are found: to provide two delayelements in the inner loop, a fourth-order modulator is required,while to provide three delay elements, a thirteenth-order modulator isobtained.The results show that in general it is better to unfold the modulatorthan to obtain the speed-up through optimizing the arithmeticoperators with the synthesis tool. Using correct pipelining/retimingis also crucial. Finally, for very high-speed implementation, usingthe structures with more delay elements is required. Also, in manycases these are more area and power efficient compared to usingoptimized arithmetic operators, despite their higher computationalcomplexity.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / This paper presents the design of an innovative approach to Frequency Division Multiplexing (FDM) for the STRICOM Hardened Subminiature Telemetry and Sensor System (HSTSS) Data Acquisition Chipset (DAC) program. An ASIC (Application Specific Integrated Circuit) is being developed by Systems & Processes Engineering Corporation (SPEC) that implements this new digital FDM approach for telemetry applications. The FDM ASIC provides six channels that are IRIG-106 compatible, and may be used in conjunction with a Delay/Repeater ASIC. Together these ASICs make a complete instrumentation system for those applications requiring very small size, simplicity of use, and low cost, e.g. munitions/armament testing.

International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / The architecture of the High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation other than CMOS technology such as Gallium Arsenide (GaAs) which has high cost and power requirements. It is more desirable to use CMOS technology with its lower power requirements and higher gate density. However, digital demodulation of high data rates in CMOS requires parallel algorithms to process the sampled data at a rate lower than the data rate. The parallel processing algorithms described here were developed jointly by NASA’s Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL). The resulting all-digital receiver has the capability to demodulate BPSK, QPSK, OQPSK, and DQPSK at data rates in excess of 300 Mega-bits per second (Mbps) per channel. This paper will provide an overview of the parallel architecture and features of the HRDR ASIC. In addition, this paper will provide an overview of the implementation of the hardware architectures used to create flexibility over conventional high rate analog or hybrid receivers. This flexibility includes a wide range of data rates, modulation schemes, and operating environments. In conclusion it will be shown how this high rate digital demodulator can be used with an off-the-shelf A/D and a flexible analog front end, both of which are numerically computer controlled, to produce a very flexible, low cost high rate digital receiver.

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / To support initiatives for cheaper, faster, better ground telemetry systems, the Data Systems Technology Division (DSTD) at NASA Goddard Space Flight Center is developing a new Very Large Scale Integration (VLSI) Application Specific Integrated Circuit (ASIC) targeted to dramatically lower the cost of telemetry frame synchronization. This single VLSI device, known as the Parallel Integrated Frame Synchronizer (PIFS) chip, integrates most of the functionality contained in high density 9U VME card frame synchronizer subsystems currently in use. In 1987, a first generation 20 Mbps VMEBus frame synchronizer based on 2.0 micron CMOS VLSI technology was developed by Data Systems Technology Division. In 1990, this subsystem architecture was recast using 0.8 micron ECL & GaAs VLSI to achieve 300 Mbps performance. The PIFS chip, based on 0.7 micron CMOS technology, will provide a superset of the current VMEBus subsystem functions at rates up to 500 Mbps at approximately one-tenth current replication costs. Functions performed by this third generation device include true and inverted 64 bit marker correlation with programmable error tolerances, programmable frame length and marker patterns, programmable search-check-lock-flywheel acquisition strategy, slip detection, and CRC error detection. Acquired frames can optionally be annotated with quality trailer and time stamp. A comprehensive set of cumulative accounting registers are provided on-chip for data quality monitoring. Prototypes of the PIFS chip are expected in October 1995. This paper will describe the architecture and implementation of this new low-cost high functionality device.

CGRAs (coarse grained reconfigurable array architectures) try to fill the gap between FPGAs and ASICs. Over three decades, the research towards CGRA design has produced number of architectures. Each of these designs lie at different points on a line drawn between FPGAs and ASICs, depending on the tradeoffs and design choices made during the design of architectures. Thus, design space exploration (DSE) takes a very important role in the circuit design process. In this work I propose the design space exploration of CGRAs can be done quickly and efficiently through crowd-sourcing and a game driven approach based on an interactive mapping game UNTANGLED and a design environment called SmartBricks. Both UNTANGLED and SmartBricks have been developed by our research team at Reconfigurable Computing Lab, UNT. I present the results of design space exploration of domain-specific reconfigurable architectures and compare the results comparing stripe vs mesh style, heterogeneous vs homogeneous. I also compare the results obtained from different interconnection topologies in mesh. These results show that this approach offers quick DSE for designers and also provides low power architectures for a suite of benchmarks. All results were obtained using standard cell ASICs with 90 nm process.

Data streaming applications, such as signal processing, multimedia applications, often require high computing capacity, yet also have stringent power constraints, especially in portable devices. General purpose processors can no longer meet these requirements due to their sequential software execution. Although fixed logic ASICs are usually able to achieve the best performance and energy efficiency, ASIC solutions are expensive to design and their lack of flexibility makes them unable to accommodate functional changes or new system requirements. Reconfigurable systems have long been proposed to bridge the gap between the flexibility of software processors and performance of hardware circuits. Unfortunately, mainstream reconfigurable FPGA designs suffer from high cost of area, power consumption and speed due to the routing area overhead and timing penalty of their bit-level fine granularity. In this dissertation, we present an architecture design, application mapping and performance evaluation of a novel coarse-grained reconfigurable architecture, named SmartCell, for data streaming applications. The system tiles a large number of computing cell units in a 2D mesh structure, with four coarse-grained processing elements developed inside each cell to form a quad structure. Based on this structure, a hierarchical reconfigurable network is developed to provide flexible on-chip communication among computing resources: including fully connected crossbar, nearest neighbor connection and clustered mesh network. SmartCell can be configured to operate in various computing modes, including SIMD, MIMD and systolic array styles to fit for different application requirements. The coarse-grained SmartCell has the potential to improve the power and energy efficiency compared with fine-grained FPGAs. It is also able to provide high performance comparable to the fixed function ASICs through deep pipelining and large amount of computing parallelism. Dynamic reconfiguration is also addressed in this dissertation. To evaluate its performance, a set of benchmark applications has been successfully mapped onto the SmartCell system, ranging from signal processing, multimedia applications to scientific computing and data encryption. A 4 by 4 SmartCell prototype system was initially designed in CMOS standard cell ASIC with 130 nm process. The chip occupies 8.2 mm square and dissipates 1.6 mW/MHz under fully operation. The results show that the SmartCell can bridge the performance and flexibility gap between logic specific ASICs and reconfigurable FPGAs. SmartCell is also about 8% and 69% more energy efficient and achieves 4x and 2x throughput gains compared with Montium and RaPiD CGRAs. Based on our first SmartCell prototype experiences, an improved SmartCell-II architecture was developed, which includes distributed data memory, segmented instruction format and improved dynamic configuration schemes. A novel parallel FFT algorithm with balanced workloads and optimized data flow was also proposed and successfully mapped onto SmartCell-II for performance evaluations. A 4 by 4 SmartCell-II prototype was then synthesized into standard cell ASICs with 90 nm process. The results show that SmartCell-II consists of 2.0 million gates and is fully functional at up to 295 MHz with 3.1 mW/MHz power consumption. SmartCell-II is about 3.6 and 28.9 times more energy efficient than Xilinx FPGA and TI's high performance DSPs, respectively. It is concluded that the SmartCell is able to provide a promising solution to achieve high performance and energy efficiency for future data streaming applications.

Demand of CO2 gas sensors is expected to continue to increase in the foreseeable future, due to an increasing awareness of air pollution and fossil fuel emissions. A truly low cost and accurate NDIR sensor has the potential of greatly benefiting the environment by an increased human awareness due to CO2 measurements. In the objective to reach these goals, a CO2 sensor core on an ASIC needs to be investigated. In this study an ASIC prototype design is tested on an FPGA and evaluated towards logic resource requirements, power analysis and estimated cost impacts towards a full ASIC. The results show that a potential ASIC implementation would have a very small cost impact on a full system design if the use of a preexisting ASIC design is utilized. Using a manufacturing process of 180 nm, the total logic implementation would require between 0.54-0.76 mm2. The cost impact of such a logic area would be around $0.025 USD per chip. The power consumption of the logical part would also be very small when compared to the various analog components of a full system design.

Restoring vision to the blind has been an objective of several research teams for a number of years. It is known that spots of light -- phosphenes -- can be elicited by way of electrical stimulation of surviving retinal neurons. Beyond this, however, our understanding of prosthetic vision remains rudimentary. To advance the realisation of a clinically viable prosthesis for the blind, a versatile integrated circuit neurostimulator was designed, manufactured, and verified. The neurostimulator provides electrical stimuli to surviving neurons in the visual pathway, affording blind patients some form of patterned vision; besides other benefits (independence), this limited vision would let patients distinguish between day and night (resetting their circadian rhythm). This thesis presents the development of the neurostimulator, an interdisciplinary work bridging engineering and medicine. Features of the neurostimulator include: high-voltage CMOS transistors in key circuits, to prevent voltage compliance issues due to an unknown or changing combined tissue and electrode/tissue interface impedance; simultaneous stimulation using current sources and sinks, with return electrodes configured to provide maximum charge containment at each stimulation site; stimuli delivered to a two dimensional mosaic of hexagonally packed electrodes, multiplexing current sources and sinks to allow each electrode in the whole mosaic to become a stimulation site; electrode shorting to remove excess charge accumulated during each stimulation phase. Detailed electrical testing and characterisation verified that the neurostimulator performed as specified, and comparable to, or better than, other vision prostheses neurostimulators. In addition, results from several animal experiments verified that the neurostimulator can elicit electrically evoked visual responses. The features of the neurostimulator enable research into how simultaneous electrical stimulation affects the visual neural pathways; those research results could impact other neural prosthetics research and devices.

<p>The purpose of the thesis was to investigate and evaluate existing algorithms for division of complex numbers. The investigation should include implementation of a few suitable algorithms in VHDL. The main application for the divider is compensation for fading in a baseband processor.</p><p>Since not much public research is done within the area of complex division in hardware, a divider based on real valued division was designed. The design only implements inversion of complex numbers instead of complete division because it is simpler and the application does not need full division, thus the required chip size is reduced.</p><p>An examination of the different kinds of algorithms that exists for real valued division was done and two of the methods were found suitable for implementation, digit recurrence and functional iteration. From each of the two classes of algorithms one algorithm was chosen and implemented in VHDL. Two different versions of the inverter were designed for each method, one with full throughput and one with half throughput. The implementations show very similar results in terms of speed, size and performance. For most cases however, the digit recurrence implementation has a slight advantage.</p>

<p>The scope for this thesis was to design a debug interface for a DSP (digital signal processor). The DSP is a research version of a Motorola 56000 that is designed for a project on asynchronous processor and for use in education.</p><p>The DSP and debug interface are controlled via a standard PC with RS232 interface equipped with Linux operation system.</p><p>In the project 4 blocks has been designed:</p><p>The first block can set the DSP core in debug mode or run mode. The second block sends a debug instruction to the DSP core, these debug instructions were prerequisite to the project. The third block enable read and write connection to the memory buses between the DSP core and the three memory blocks. The forth block can override the control signals to the memories from the DSP core.</p><p>The project also uses an UART for interpreting and sending control signals and data between the different blocks and the computer.</p><p>A text terminal program for Linux has also been programmed for handling the PC side communication.</p><p>The hardware has been constructed and tested together with a dummy DSP core and dummy memories, but it has not been tested together with the live DSP core.</p><p>The Linux program has been tested the same way and seems to do what it's supposed to, though it leaves a lot work to be easy to handle.</p>