Mental illness is currently diagnosed using subjective observational criteria as outlined in the 5th Edition of the Diagnostic and Statistical Manual (DSM-V), yet many have argued for the medicalization of the diagnosis of mental illness by incorporating biomedical and neuroanatomical criteria. The following literature review explores the neural circuit responsible for regulating emotion, as well as the structural and chemical alterations to this circuit that have been shown to correlate with aggressive and/or violent behaviors characteristic of certain types of mental illness. The neural circuit regulating emotion is comprised of the prefrontal cortex, the subcortical limbic system, the dopaminergic pathway, the serotonergic pathway, catecholaminergic neurons, and GABAergic neurons. Alterations to these structures or chemicals have been associated with major depressive disorder, suicidal ideations, substance use disorders, schizophrenia, and personality disorders. Medicalization of mental illness has the potential to serve two purposes – first, to standardize diagnosis and treatment of mental illness, and second, to decrease the stigma often associated with mental illness – and to improve outcomes for those patients living with mental illness.

In mammals, circadian rhythms are controlled by an endogenous clock located in the suprachiasmatic nucleus (SCN). The SCN is part of a wake-promoting pathway in adults involving the dorsomedial hypothalamus (DMH) and locus coeruleus (LC), but little is known about how this circuit develops. Therefore, we examined the neural mechanisms underlying the development of circadian and ultradian sleep-wake rhythms. Circadian rhythms of sleep and wakefulness are exhibited by rats at postnatal day (P)2, but the influence of forebrain structures, including the SCN, has not been examined. In Experiment 1, although precollicular transections at P2 did not alter day-night differences in sleep and wakefulness, transections at P8 did eliminate these differences. In contrast, in Experiment 2, SCN lesions eliminated day-night differences in sleep and wakefulness at P2. These results suggest that the SCN exerts a humoral influence in newborns and gains neural control over brainstem structures over the first postnatal week. Based on the results of Experiments 1 and 2, we hypothesized that neural connections among the SCN, DMH, and LC develop over the first postnatal week. In Experiment 3, we used fluorescent tracers to reveal that connections within this circuit are strengthened and elaborated--and also become bidirectional--between P2 and P8. The results of Experiment 3 indicate that the SCN receives feedback from the LC. To explore the functional mechanisms by which the SCN receives this feedback, in Experiment 4, we deprived pups of sleep at P8 and used cFos to visualize brain areas that became active as a result of forced wakefulness. Our findings in intact pups and those injected with DSP-4, a neurotoxin that targets noradrenergic LC terminals, suggest that forced wakefulness activates the LC, which subsequently activates the DMH and SCN. After connectivity among the SCN, DMH, and LC is established, we tested the functional role of each nucleus in the modulation of sleep and wakefulness. Infants cycle rapidly between states of sleep and wakefulness, resulting in fragmented bouts. Over development, these sleep and wake bouts consolidate and circadian rhythms become evident. Analyses of the statistical distributions of sleep and wake bouts have revealed dramatic changes in the dynamics of sleep-wake activity. Sleep bouts follow an exponential distribution throughout development. In contrast, wake bouts initially follow an exponential distribution, but transition to a power-law distribution around P15. In Experiments 5, 6, and 7, we explored the contributions of the LC, SCN, and DMH, respectively, to this developmental transition. We found that lesions of each area prevented the emergence of power-law wake behavior. Lesions of the SCN and DMH also prevented the expression of nocturnality. Altogether, these findings reveal that neural connections between the SCN and brainstem develop over the first postnatal week. After this connectivity is established, the SCN-DMH-LC pathway is critical for the normal expression of power-law wake behavior and circadian rhythmicity. We suggest that the development of the SCN-DMH-LC circuit is critical for pups to regulate arousal and gain independence from the mother and littermates.

This thesis investigates the development of a machine which is termed as singly salient reluctance (SSR) motor and its drive system. The stator of SSR motor is identical to that of a conventional induction motor or any other ac machine. Its rotor has salient poles with internal flux barriers or flux guides. This research covers the detailed designs of the SSR motors and their magnetic circuit analysis using finite element method (FEM). The parameters which are important for designing the SSR motor are investigated. This investigation resulted in designs which have low manufacturing cost as well as high torque per ampere, efficiency and power factors. This thesis also researches the different drive system for the SSR motor. The SSR motor is tested as a variable speed drive with closed loop control and supplied with dc source. Therefore for this purpose a controller system is designed and built. In addition, the SSR motor supplied by ac source using open loop control is also tested for synchronous operation. Some of the proposed designs are built and their performance compared with their predicted analysis. The SSR motors showed a competitive performance compared with equivalent induction motor in both efficiency and power factor. However the validity of the theoretical designs is assessed by comparing them with experimental results. Quite good agreement between experimental and theoretical evaluations has been achieved. In addition, suggested further improvements for SSR motors and drive systems are discussed. / Doctor of Philosophy (PhD)

Les outils informatiques prennent une place de plus en plus importante dans la conception de circuits VLSI. Les langages de description de matériel constituent l'interface entre ces outils et les utilisateurs. Parmi ceux-ci, il existe un standard qui est VHDL, destiné à la description de systèmes numériques. Actuellement une extension analogique est en cours de normalisation. Les deux premiers chapitres de cette thèse sont consacrés l'un aux langages de description de matériel et à une présentation de VHDL, ainsi que des remarques et analyses à propos de son extension analogique. Le second thème de cette thèse est la mise en évidence de l'importance de la simulation en mode mixte numérique-analogique. Le troisième chapitre présente les principes généraux de la simulation mixte; différentes implémentations de simulateurs mixtes sont présentés. Enfin, le dernier chapitre est consacré à la réalisation d'un simulateur mixte dont la partie numérique est un simulateur VHDL. Cette réalisation repose sur une approche de description qui permet d'utiliser la souplesse de description structurelle de VHDL pour des systèmes analogiques et mixtes

L'accroissement de la densité d'intégration des circuits intégrés exige des moyens de contrôle d'une extrème précision. La microscopie électronique à balayage en contraste de potentiel convient particulièrement. La thèse présente tous les aspects: organisation, observabilité, méthodes d'observation, modes de traitement et les applications à la mise au point de circuits prototypes, l'analyse des défaillances, le contrôle de qualité, la recherche des limites de fonctionnement, la restructuration. Discussion de la nécessité du développement de méthodologies d'utilisation

<p>Today’s microprocessors with millions of transistors perform high-complexity computing at multi-gigahertz clock frequencies. The ever-increasing chip size and speed call for new methodologies in clock distribution network. Conventional global synchronization techniques exhibit many drawbacks in the advanced VLSI chips such as high-speed microprocessors. A significant percentage of the total power consumption in a microprocessor is dissipated in the clock distribution network. Also since the chip dimensions increase, clock skew management becomes very challenging in the framework of conventional methodology. Long interconnect delays limit the maximum clock frequency and become a bottleneck for future microprocessor design. In such a situation, new alternative techniques for synchronization in system-on-chip are demanded.</p><p>This thesis presents new alternatives for traditional clocking and synchronization methods, in which, speed and power consumption bottlenecks are treated. For this purpose, two new techniques based on mesochronous synchronization and resonant clocking are investigated. The mesochronous synchronization technique deals with remedies for skew and delay management. Using this technique, clock frequency up to 5 GHz for on-chip communication is achievable in 0.18-<em>μ</em>m CMOS process. On the other hand the resonant clocking solves significant power dissipation problem in the clock network. This method shows a great potential in power saving in very large-scale integrated circuits. According to measurements, 2.3X power saving in clock distribution network is achieved in 130-nm CMOS process. In the resonant clocking, oscillator plays a crucial role as a clock generator. Therefore an investigation about oscillators and possible techniques for jitter and phase noise reduction in clock generators has been done in this research framework. For this purpose a study of injection locking phenomenon in ring oscillators is presented. This phenomenon can be used as a jitter suppression mechanism in the oscillators. Also a new implementation of the DLL-based clock generators using ring oscillators is presented in 130-nm CMOS process. The measurements show that this structure operates in the frequency range of 100 MHz-1.5 GHz, and consumes less power and area compared to the previously reported structures. Finally a new implementation of a 1.8-GHz quadrature oscillator with wide tuning range is presented. The quadrature oscillators potentially can be used as future clock generators where multi-phase clock is needed.</p> / Report code: LiU-TEK-LIC-2006:22

A method and apparatus are presented for generating suppressed carrier digital clock signals. These clock signals have the advantage of being broad band in nature and thus exhibiting lower power spectral density. Structures or systems utilizing such clock signals would be less likely to create electromagnetic noise of sufficient intensity to interfere with radio frequency systems and services. The apparatus requires only digital logic devices, rather than the analog devices required for frequency- or phase-modulated spread spectrum clock generators. The method provides the opportunity to synchronously demodulate the clock, thus restoring the original narrow band clock signal where required. The apparatus was implemented in a programmable gate array using 20 MHz and 33.33 MHz fundamental clocks. Measurements of the resulting electronic spectra and clock jitter are reported. / Graduation date: 1999

This thesis describes two programs for generating tests for digital circuits that exploit several kinds of expert knowledge not used by previous approaches. First, many test generation problems can be solved efficiently using operation relations, a novel representation of circuit behavior that connects internal component operations with directly executable circuit operations. Operation relations can be computed efficiently by searching traces of simulated circuit behavior. Second, experts write test programs rather than test vectors because programs are more readable and compact. Test programs can be constructed automatically by merging program fragments using expert-supplied goal-refinement rules and domain-independent planning techniques.

Circuit breaker is an important interrupting device in power system network. It usually has a lifetime about 20 to 40 years. During breaker's service time, maintenance and inspection are imperative duties to achieve its reliable operation. To automate the diagnostic practice for circuit breaker operation and reduce the utility company's workload, Wavelet based analysis software of circuit breaker operation is developed here. Combined with circuit breaker monitoring system, the analysis software processes the original circuit breaker information, speeds up the analysis time and provides stable and consistent evaluation for the circuit breaker operation.

In this thesis, the first section will talk about how to implement the software development environment for 8bit microprocessor, including Compiler, Assembler, and Debugging mechanism etc. The design of Debugging mechanism is based on in-circuit emulator. In-circuit emulator is a common debugging technique for microprocessor. The designed ICE contains hardware implement and debugging software for it in this thesis. ICE hardware is a control circuit from TAP Controller, IEEE 1149.1 std. and it control the scan cells on the data bus. The Debugging software uses JTAG port, IEEE 1149.1 std., to insert debug instruction from PC to ICE hardware. In this thesis, the second section will focus on the process of integrating ICE hardware circuit and software debugger issued by two ways, our own design version and business suit debugging software support. The examples are not only integrating our LAB¡¦s 32bit microprocessor and ICE hardware, but also verifying software debugger to control ICE circuit by FPGA to prove above two methods are work.