Le graphène, une couche monoatomique de carbone, est étudié comme matériau pourconstruire ou encapsuler des biocapteurs afin d’adresser les problèmes de durabilitérencontrés avec les implants intra-corticaux. Ces derniers sont des outils essentiels pour lesprojets médicaux de neuro-réhabilitation afin d’enregistrer les signaux de motoneuronesuniques dans le cerveau. Les implants actuels sont invasifs et leur efficacité est limitée dans letemps par la réaction de rejet des tissus. En combinant une synthèse de graphène optimiséeà cet usage (monocouche continue sur plusieurs cm²) et son intégration dans des capteursélectroniques ultra-sensibles, protégés par des polymères bioactifs, cette thèse propose unenouvelle approche pluridisciplinaire pour construire des implants offrant une meilleurebioacceptance. Au moyen de méthodes d’intégration innovantes et d’études ducomportement du graphène in-vivo et in-vitro, nous évaluons expérimentalement lafaisabilité d’intégration du graphène dans les futures interfaces cerveau machines pour desprojets médicaux au long terme. / Graphene, an atomically thin layer of carbon, is investigated as a biosensing andcoating material in order to address the long term durability issues of invasive intracorticalimplants. These devices are essential tools to record specific single motor neurons activity formedical applications aiming at healing neural injuries. Today’s implants suffer from their highinvasiveness. It is responsible for local inflammation that leads to the failure in unique neuronsactivity recordings in the motor cortex on a long term basis. By combining a monolayergraphene growth and transfer with an ultra-sensitive electronic integration and a biochemicalfunctionalization, this thesis proposes a new multidisciplinary approach to build intracorticalimplants with an improved bioacceptance. By using innovative methods of grapheneintegration in implants, and in-vitro and in-vivo studies to assess the reactions of living tissuesto graphene, we provide an overview of graphene’s potential contribution to future brainmachine interfaces for long term medical projects.

Actuellement, l'étude et le développement d'oxydes à commutation de résistance pour des dispositifs mémoires (Resistive RAM, ou ReRAM) constituent un domaine d'activité intense sur le plan international. Les ReRAMs sont des structures MIM (Métal-Isolant-Métal) dont la résistance peut être modulée par l’application d’une tension. A ce jour, les mécanismes qui régissent la transition de résistance dans les dispositfs ReRAM sont toujours l’objet de débats. Le travail développé dans cette thèse représente une contribution au développement des mémoires ReRAM à base de HfO2. Nous nous intéressons plus particulièrement aux ReRAMs « à pont conducteur » (Conducting Bridge RAM, ou CBRAM) pour lesquelles la transition de résistance est provoquée par la diffusion du métal d’anode. Nous cherchons à améliorer la compréhension des phénomènes qui contrôlent le passage d’un état isolant à un état conducteur. Dans ce cadre, notre travail se focalise sur l’influence des métaux d'électrodes. Le rôle de l’anode et de la cathode sont précisés. Un modèle qualitatif est présenté permettant d’expliquer la commutation de résistance. Nous discutons également des mécanismes de conduction dans l’état de faible résistance. Enfin, l’impact de la structure de l’oxyde est étudié. / The Resistive Random Access Memory (ReRAM) technology is attracting growing interest as a potential candidate for the next generation of nonvolatile memories. ReRAMs are MIM (Metal-Insulator-Metal) devices whose resistance can be tuned by voltage bias. Today the physical mechanisms at the origin of resistance switching are not yet fully understood and are still under debate. In the present work, we are interested in HfO2-based ReRAMs, with a focus on Conducting Bridge RAM (CBRAM) devices in which resistance transition is ascribed to anode metal diffusion. Our goal is to better identify phenomena which govern the high to low resistance transition. In this context, we study the impact of different metal electrodes. The role played by the anode and the cathode is elucidated. A qualitative model describing resistance transition is proposed. Conduction mechanisms in the low resistive state are also discussed. Finally, the impact of oxide structure is studied.

Afin d’optimiser les composants de l’industrie de la microélectronique, il est essentiel d’établir le lien entre la texture cristallographique des matériaux constitutifs et leurs propriétés électriques, thermiques et mécaniques. Ainsi, il est nécessaire de disposer d’outils capables de cartographier la morphologie et l’orientation cristallographique des grains à l’échelle nanométrique. La technique ACOM, implémentée sur un Microscope Electronique en Transmission (MET), permet d’obtenir ces informations en exploitant les figures de diffraction électronique. Dans cette thèse, les capacités de cette technique sont évaluées, à la fois pour déterminer la microtexture de matériaux confinés dans quelques dizaines de nanomètres, et pour répondre aux problématiques associées à la fabrication de nouveaux circuits. Cette étude montre dans un premier temps l’importance de l’optimisation des conditions opératoires du MET afin de diminuer les erreurs d’indexation. Des analyses quantitatives de microtexture sont ensuite menées sur des films minces de siliciures de nickel-platine pour différents dopage du substrat, concentration en platine, et température de recuit. Enfin, le cas d’une superposition de signaux de diffraction observé lorsque plusieurs grains sont contenus dans l’épaisseur de l’échantillon est étudié. Les résultats montrent que les erreurs d’indexation restent rares dans ce cas et que les grains de plus large fraction volumique sont majoritairement sélectionnés par l’algorithme d’indexation. Une méthode est alors proposée pour traiter la totalité de l’information détectée dans les clichés de diffraction. Elle s’appuie sur l’indexation successive des orientations cristallographiques après soustraction préalable des réflexions associées à l’orientation précédemment indexée. Les capacités de cet outil en termes de caractérisation de la morphologie des grains superposés sont finalement comparées à deux autres techniques basées sur la reconstruction d’images en champ sombre et sur la factorisation en matrices non-négatives. / The development of advanced nodes in microelectronics requires to understand the impact of crystal size and orientation on the electrical, thermal and mechanical properties of materials. New tools have been developed to map the grains orientation and morphology of nanometer-scaled structures. Among them, the Automated Crystal Orientation Mapping technique used on a Transmission Electron Microscope (ACOM-TEM) is based on the indexation of electron diffraction patterns. The aim of this study was to evaluate the abilities and limitations of the ACOM-TEM technique for the characterization of microelectronics-related materials. Consequently, its ability to analyze nano-sized materials and the possibility of answering problematics related to microelectronics front-end fabrication challenges were investigated. The study highlighted in the first place the importance of the TEM illumination settings. The results showed that minimizing the electron probe convergence angle even at the cost of a larger size has decreased mis-indexation issues. These optimum settings were used to perform quantitative texture analysis of NiPt-silicide thin films. Finally, the case of superimposed diffraction patterns related to overlapping grains was analyzed. Experiments showed that mis-indexing remains limited despite the superimposition and that grains with larger fraction volume were preferentially selected by template matching. A dedicated method was also proposed to overcome crystal overlapping issues. The approach is based on iterative re-indexation of diffraction patterns after subtraction of the reflections related to the previous ACOM best match. Considering the same diffraction patterns data-set, the capabilities of this method to recover the grains size and morphology were compared to two recent techniques based respectively on the analysis of virtual dark field (VDF) images and non-negative matrix factorization (NMF).

abstract: Temporary bonding-debonding of flexible plastic substrates to rigid carriers may facilitate effective substrate handling by automated tools for manufacture of flexible microelectronics. The primary challenges in implementing practical temporary bond-debond technology originate from the stress that is developed during high temperature processing predominately through thermal-mechanical property mismatches between carrier, adhesive and substrate. These stresses are relaxed through bowing of the bonded system (substrate-adhesive-carrier), which causes wafer handling problems, or through delamination of substrate from rigid carrier. Another challenge inherent to flexible plastic substrates and linked to stress is their dimensional instability, which may manifest itself in irreversible deformation upon heating and cooling cycles. Dimensional stability is critical to ensure precise registration of different layers during photolithography. The global objective of this work is to determine comprehensive experimental characterization and develop underlying fundamental engineering concept that could enable widespread adoption and scale-up of temporary bonding processing protocols for flexible microelectronics manufacturing. A series of carriers with different coefficient of thermal expansion (CTE), modulus and thickness were investigated to correlate the thermo-mechanical properties of carrier with deformation behavior of bonded systems. The observed magnitude of system bow scaled with properties of carriers according to well-established Stoney's equation. In addition, rheology of adhesive impacted the deformation of bonded system. In particular, distortion-bowing behavior correlated directly with the relative loss factor of adhesive and flexible plastic substrate. Higher loss factor of adhesive compared to that of substrate allowed the stress to be relaxed with less bow, but led to significantly greater dimensional distortion. Conversely, lower loss factor of adhesive allowed less distortion but led to larger wafer bow. A finite element model using ANSYS was developed to predict the trend in bow-distortion of bonded systems as a function of the viscoelastic properties of adhesive. Inclusion of the viscoelasticity of flexible plastic substrate itself was critical to achieving good agreement between simulation and experiment. Simulation results showed that there is a limited range within which tuning the rheology of adhesive can control the stress-distortion. Therefore, this model can aid in design of new adhesive formulations compatible with different processing requirements of various flexible microelectronics applications. / Dissertation/Thesis / Ph.D. Chemical Engineering 2011

Este trabalho apresenta um gerenciador de ferramentas para projeto de circuitos integrados, o sistema TENTOS, agora desenvolvido para o ambiente MS-WINDOWSTM. O ambiente TENTOS é um sistema aberto, isto é, permite a fácil inclusão de novas ferramentas em tempo de execução do gerenciador, tornando-o desta forma sempre atual em relação as ferramentas existentes. Inicialmente será feita uma breve descrição de alguns dos gerenciadores existentes, tanto os desenvolvidos com finalidades comerciais como os do meio acadêmico Em seguida, será apresentado um histórico sobre a evolução do sistema TENTOS, da sua versão inicial até a sua versão atual. Em uma etapa seguinte será descrito o estado atual do sistema TENTOS, isto é, suas características principais a estrutura dos menus, os arquivos de configuração do sistema. como incluir novas ferramentas, arquivos de tecnologia, a configuração standard do sistema, quais ferramentas acompanham o TENTOS; como funciona a execução das ferramentas. Concluída a apresentação do sistema TENTOS, sendo apresentados exemplos que ilustram as etapas de desenvolvimento de um projeto de circuito integrado utilizando o sistema TENTOS. / This dissertation presents a tool mana ger for integrated circuit design, the TENTOS system, now developed for the MS-WINDOWSTM environment. The TENTOS package is an open system. that allows an eas y inclusion of new tools in the execution time of the manager, allowing an easy and constant updating of tools that are integrated into the package. Firstly, a short description of existing frameworks will be shown b y including commercial and academics systems. Secondly, a brief historical of TENTOS evolution system will be presented. Following thet description the present state of the TENTOS s ystem will be described which comprises: its main characteristics: the structure of menus; system configuration files; how to include new tools and technology files; the standard system configuration, which tools are available into the TENTOS and how they are executed. Finally some examples on how to use the TENTOS system will be shown.

Esse trabalho apresenta um estudo sobre os efeitos de radiação em circuitos analógicos de baixa e ultra baixa potência e tensão, identificando as fragilidades destes circuitos (e das respectivas técnicas de projeto) quando aplicados em ambientes radioativos, como, por exemplo, os circuitos em satélites, e em equipamentos de instalações nucleares. Foram realizados estudos de caso, via simulação elétrica utilizando o software HSPICE, considerando os efeitos de degradação elétrica correspondentes a doses de radiação acumulada de até 500krad(Si), além de eventos singulares considerando circuitos de baixa tensão e potência projetados para a tecnologia IBM (GF) de 130nm. Pôde-se observar que o uso de transistores de óxido mais fino, apesar de afetar negativamente o consumo estático, é recomendado para as aplicações estudadas, devido a menor sensibilidade à radiação. Ainda, foi discutido o aumento dos caminhos de fuga de corrente devido ao uso de layout distribuído. Possibilidades e estratégias de mitigação foram discutidas. Por fim, obteve-se um conjunto de sugestões e informações para auxiliar o projetista de circuitos de baixo consumo a obter soluções robustas à radiação. / This work studies the radiation effects in low-power and ultra-low power analog circuits, identifying the fragility of such circuits (and associated design techniques) when employed in radioactive environments, as for example, in satellites and nuclear facilities. Case studies were carried out using HSPICE software for electrical simulation of cumulative radiation effects, corresponding to doses up to 500krad(Si), as well as for single events simulation. We showed that, the use of thin oxide (core) MOSFETS, though increasing the static consumption, is recommended for the studied applications, because they are less sensitive to radiation. Then, we discussed the increase of current leakage paths by the distributed layout style. Mitigation strategies were also discussed. Finally, we obtained a set of suggestions and information to guide the designers of low power analog circuits towards obtaining radiation robust solutions.

Dans les noeuds technologiques avancés ainsi que les technologies dérivées, des règles de dessin de plus en plus aggressives sont nécessaires. Cela conduit à une complexification des structures dans les circuits intégrés actuels. De telles structures posent un défi important aux procédés de fabrication, notamment les étapes dites de patterning que sont la lithographie et la gravure. Afin d'améliorer et d'optimiser ces structures, les designers se basent sur les règles et connaissances qu’ont les ingénieurs de leurs procédés. Ces règles ont besoin d'être alimentées par des informations dimensionnelles et structurelles de plus en plus complexes : configurations de type bord arrondi, distance entre deux bouts de lignes, rétrecissement de ligne, etc. La métrologie doit évoluer afin que les ingénieurs soient capables de mesurer et quantifier les dimensions des structures les plus complexes dans le but d'estimer la variabilité de leur procédé. Actuellement la variabilité est principalement estimée à partir de données issues du suivi en ligne de structures simples car elles sont les seules à garantir une mesure robuste et reproductible. Mais, elles peuvent difficilement être considérées comme représentatives du procédé ou du circuit. Utiliser la métrologie par CD-SEM pour mesurer des structures complexes de manière robuste est un défi technique. La création de recettes de mesures est complexe, nécessite un temps non négligeable et ne garantit pas une mesure stable. Cependant, une quantité importante d'informations est contenue dans l'image SEM. Les outils d'analyses fournis par les équipementiers permettent aujourd'hui d'extraire les contours SEM d'une structure présente dans l’image. Ainsi, le CD-SEM prend des images et la partie métrologie est réalisée hors ligne afin d'estimer la variabilité. Cette thèse vise à proposer aux ingénieurs de nouvelles possibilités de métrologie dimensionnelle afin de l’appliquer pour le contrôle des structures les plus complexes. Les contours SEM sont utilisés comme source d’information et exploités pour générer de nouvelles métriques. / In advanced technological nodes as well as derived technologies, aggressive design rules are needed. This leads to a complexity of structures in the current integrated circuits. Such structures pose a significant challenge to chip manufacturing processes, in particular patterning steps of lithography and etching. In order to improve and optimize these structures, designers need to rely on the rules and knowledge that engineers have about their processes. These rules need to be fed by complex dimensional and structural information: corner rounding, tip to tip distances, line end shortening, etc. Metrology must evolve so that engineers are able to measure and quantify the dimensions of the most complex structures in order to assess the process variability. Currently the variability is mainly quantified using data from the inline monitoring of simple structures as they are the only ones to guarantee a robust and reproducible measurement. But, they can hardly be considered as representative of the process or the circuit. Using CD-SEM metrology to measure complex structures in a robust way is a technical challenge. The creation of measurement recipes is complex, time consuming and does not guarantee a stable measurement. However, a significant amount of information is contained in the SEM image. The analysis tools provided by the equipment manufacturers allow to extract the SEM contours of a structure present in the image. Thus, the CD-SEM takes images and the metrology part is performed offline to estimate the variability.This thesis offers engineers new possibilities of dimensional metrology in order to apply it for process control of complex structures. SEM contours are used as a source of information and used to generate new metrics.

De nombreuses techniques de caractérisation sont utilisées dans les industries de la microélectronique dans le but d’inspecter et analyser les circuits. Actuellement, la réduction des dimensions des transistors, l’implémentation d’alliage de silicium-germanium (SiGe) et l’ingénierie des déformations, nécessitent de développer une métrologie innovante des champs de déformations induits par les procédés de fabrication. Ces techniques non-destructives et rapides de caractérisation des déformations doivent être aussi capables d’analyser des nanostructures directement en ligne de production. Dans ce contexte, nous avons évalué les performances de la diffraction de rayons-X haute résolution (HRXRD) et de la spectroscopie Raman à mesurer des déformations, et nous avons proposé une méthodologie adaptée aux exigences de la métrologie.Les équipements industriels de HRXRD développés pour la métrologie, sont aptes à mesurer la déformation de couches nanométriques de SiGe, avec une grande sensibilité (< 10-4). Néanmoins, pour des structures complexes comme les transistors planaires, la complexité du champ de déformation requière la mesure et l’analyse approfondie de cartographies de l’espace réciproque (RSM). Nous avons alors montré l’intérêt et les performances des RSM pour la caractérisation des déformations dans des réseaux de transistors pMOS. Pour ce faire, une méthode inverse a été développée, consistant à simuler des RSM à partir d’une modélisation mécanique des champs de déformation. Différents modèles ont été explorés et un très bon accord entre les RSM mesurées et simulées est établi. Le champ des déformations extrait par cette méthode est corrélé avec succès à celui mesuré par la technique d’holographie électronique en champ sombre, démontrant ainsi l’analyse fine des champs des déformations de pMOS par HRXRD.La spectroscopie µ-Raman a aussi été identifiée comme étant une candidate prometteuse pour l’industrie, du fait de sa résolution spatiale sub-micrométrique et d’une grande sensibilité sur des structures nanométriques. Elle permet de déterminer de manière simultanée l’état de déformation et la composition moyenne d’un film de SiGe de quelques nanomètres d’épaisseur. Ainsi, la spectroscopie µ-Raman a alors permis de révéler que le procédé de condensation, critique pour la création du canal en SiGe contraint des transistors de technologie avancée, induit une inhomogénéité de composition en germanium dans le film de SiGe. Enfin, la résolution spatiale de la spectroscopie µ-Raman et de la spectroscopie Raman exaltée par effet de pointe (TERS) a été déterminée par comparaison de mesures avec des simulations. Ces résultats montrent les évolutions attendues pour répondre aux exigences de l’industrie de la microélectronique.Finalement, une méthodologie industrielle d’HRXRD permettant de suivre en ligne l’évolution du champ de déformation pendant les procédés de fabrication est développée. La méthode principale utilise une librairie de RSM simulées pour toute une série de structures avec des géométries, des compositions en germanium et des paramètres de déformation variables. Les RSM mesurées sont ensuite associées de manière sélective aux RSM simulées inclues dans la librairie, fournissant simplement et rapidement une géométrie et un champ des déformations comme données de sortie, paramètres pouvant être ajustés par des itérations ultérieures si nécessaire. Grâce au développement d’un logiciel (DeusX), qui traite et simule les RSM, l’ensemble de la procédure est capable de suivre, détecter et localiser automatiquement des variations faibles de déformation induites par les étapes de fabrication. L’ensemble des résultats démontrent que la procédure est compatible avec les exigences industrielles : rapidité, robustesse et simplicité. Ce travail est ainsi une avancée majeure vers l’utilisation des RSM pour le suivi industriel en ligne des déformations. / For many years, characterization techniques have been used in the microelectronic industry in order to probe and analyze integrated components. Nowadays the critical downscaling of transistors and implementation of new materials and methods, such as silicon-germanium (SiGe) and strain engineering, induce the necessity of developing innovative metrology in order to monitor the fabrication processes at each step. In this context, there is a need for non-destructive and fast strain characterization techniques, capable of in-line analysis of nano-structures. Within that framework, the capabilities of High Resolution X-Ray Diffraction (HRXRD) and Raman spectroscopy for strain measurements is evaluated and a methodology tailored to in-line metrology constraints is proposed.Industrial HRXRD equipment, developed for an in-line strain metrology have demonstrated their ability to measure strain in SiGe thin films of only a few nanometers thick, with a great sensitivity (< 10-4). Nonetheless, when it comes to advanced structures, such as planar transistors, the strain field complexity requires the measurement and the thorough analysis of Reciprocal Space Mappings (RSM). In this study, we demonstrate the interest and capability of RSM for the characterization of strained structures for gratings of pMOS transistors. A reverse method that consists in using a strain field model to reproduce the measured RSMs is used. The benefit of using different mechanical models is explored and a very good agreement between experimental and simulated RSM’s is established. Strain field extracted by this method is successfully correlated to the one measured by Dark-Field Electron Holography (DFEH) technique, emphasizing the capability of HRXRD for pMOS strain field investigation.Alongside, µ-Raman spectroscopy was also identified to be a promising candidate for the industry, due to a sub-micrometers spatial resolution and a low detection threshold. It enables to determine simultaneously the strain state and the average composition of SiGe thin films down to the nanometer scale. Thereby, µ-Raman reveals that a condensation process, critical to create a strained SiGe channel for advanced transistor technology, induces a germanium composition inhomogeneity in the SiGe thin films. To go further, the spatial resolution of µ-Raman and Tip-enhanced Raman Spectroscopy (TERS) techniques is investigated by comparing the measurements with simulations, highlighting that there is still some way to go before fulfilling the demands of the microelectronics industry.Finally, a HRXRD methodology is developed in order to follow the strain field evolution all along process steps in a manufacturing environment. The main method uses a large library computed for a bunch of structures with varying geometries, germanium content and strain parameters. Then the measured RSMs are selectively matched to the simulated RSMs within the library, providing in a simple and a quick way a close corresponding geometry and strain field as an output, which could then be refined by iteration if necessary. Thanks to a homemade software (DXtract), that processes and simulates the RSMs, the whole procedure is automated and is capable to follow, detect and localize even the small strain variations induced by the manufacturing steps. In addition, all the results demonstrate that the procedure is compatible with industrial constraints, meaning fast, robust and easy to operate. This work is therefore a major step towards the use of RSM for in-line monitoring, which is undoubtedly a relevant technique for industrial strain metrology.

Este trabalho propõe e avalia uma nova abordagem para projeto de circuitos dedicados utilizando matrizes pré-difundidas. A principal vantagem desta abordagem, denominada Marcela, reside na decomposição lógica do circuito a ser implementado em termos de primitivas disponíveis na matriz escolhida. Aplicando-se tal procedimento, alcança-se grande flexibilidade em termos de posicionamento e roteamento, levando a uma melhor taxa de ocupação. Primeiramente, é feito um levantamento das abordagens para pré-difundidos correntemente encontradas e uma taxonomia baseada nas características mais relevantes é definida. As principais características da metodologia TRANCA são também mostradas. Leiautes gerados com os módulos TRAMO e TRAGO são analisados e algumas modificações na metodologia são sugeridas, visando uma exploração mais eficiente dos dois níveis de metal. As bases para o desenvolvimento da abordagem Marcela são então descritas. A abordagem consiste de uma nova arquitetura para pré-difundidos e uma estratégia específica de ocupação. As principais características da matriz de propósito geral Marcela, primeira a ser definida, são a ausência de canais de roteamento, com as conexões sendo realizadas sobre as células, e a utilização de quatro tipos de células básicas, cada uma dedicada à implementação de uma função lógica primitiva. As células básicas estão organizadas em unidades básicas, as quais são repetidas regularmente para formar a matriz, numa abordagem denominada mar de células. O problema do assinalamento de células e suas particularidades são solucionados utilizando-se uma combinação entre alocação sequencial e técnicas de particionamento. Primeiro, é alocada a mínima superfície da matriz capaz de comportar o circuito em questão, numa fase chamada pré-assinalamento. Na fase de otimização, partições são geradas respeitando a integridade das unidades básicas e trocas de células são realizadas entre os blocos de cada nova partição, em dois passos: trocas individuais, enquanto o bloco de destino não estiver cheio, e trocas de pares. Para o roteamento, foi desenvolvida no CPGCC/UFRGS uma ferramenta específica para ser utilizada em leiautes gerados segundo a metodologia TRANCA. Esta ferramenta, denominada MARTE [JOH 92a][JOH 92b], emprega o algoritmo de Lee básico com algumas modificações, tal como a geração de doglegs para trocas entre trilhas adjacentes. Com a finalidade de validar a abordagem, foram implementados alguns circuitos utilizando a abordagem Marcela e uma abordagem sea-of-gates tradicional. Para circuitos pequenos, tal como um flip-flop D, Marcela produziu uma melhor distribuição de conexões, a qual resulta em aumento da transparência. Porém, a taxa de ocupação encontrada foi menor do que a do circuito projetado com sea-of-gates. Por outro lado, para circuitos de complexidade maior, a área ocupada pode resultar bem menor do que no caso de se usar sea-of-gates, desde que sejam realizadas transformações lógicas apropriadas sobre a descrição equivalente Marcela ou uma matriz conveniente seja escolhida. Exemplos de leiautes desenvolvidos mostram que taxas de ocupação tão altas quanto 75% são atingidas. Finalmente, da observação de circuitos gerados automaticamente, foram tiradas conclusões sobre modificações na arquitetura da matriz e nos algoritmos, de forma a melhorar as taxas de ocupação para qualquer tipo de circuito. / This work proposes and evaluates a new approach for the design of ASICs using prediffused masterslices. The main advantage of this approach, called Marcela, relles on logic decomposition of the circuit to be implemented into the chosen masterslice available primitives. By applying this procedure, a great placement and routing flexibility is achieved, thus leading to a better transistor utilization rate. First, a survey on current prediffused approaches is done and an specific taxonomy is defined based on the main important features encountered. Also the main features of TRANCA methodology are shown. Layouts generated using TRAGO and TRAMO modules are analyzed and some modifications in the methodology are suggested, in order to better exploit both first and second metal layers. Marcela approach development basis are described. The approach consists of a new prediffused architecture and an specific occupation strategy. The main architectural features of the general purpose Marcela masterslice are the absence of routing channels, with the connections running over the cells, and the utilization of four types of basic cells, each of them dedicated to perform one primitive logic function. Basic cells are organized into basic units, which are spread a11 over the masterslice, in a so called sea-of-cells approach. The assignment problem and its peculiarities are solved by using a combination of sequential cell allocation and quadrature partition techniques. But first of all, a minimum masterslice area is allocated in a phase called preassignment. In the optimization phase, partitions are generated respecting basic units integrity and cell interchanges are applied to each new partition, following two steps: individual changes, while the target block is not, full. and pairwise interchange. For the routing problem, an specific tool has been developed at CPGCC/UFRGS for any module generator in which TRANCA methodology is applied. This tool, called MARTE [JOH 92a][JOH 92b], employs a basic Lee algorithm with some modifications as dogleg generation for changes between adjacent tracks. In order to validate the approach, some circuits have been implemented using a traditional sea-of-gates and Marcela approaches. For small circuits, as a D flip-flop, Marcela approach has produced a better wiring distribution, which results in increase of transparency. But the occupation rate was found to be smaller than that of the sea-of-gates approach. On the other hand, for more complex circuits the amount of used area can be smaller than that of sea-of-gates case, since appropriate logic transformations are applied to the Marcela logic equivalent or a well suit masterslice is used. Implemented examples show that utilization rates as high as 0.75 are achieved. Finally, from the observation of automatically generated layouts some modifications in masterslice architecture and in the algorithms are figured out.

Neste trabalho é desenvolvida uma ferramenta de dimensionamento de portas lógicas para circuitos integrados, utilizando técnicas de otimização de problemas baseadas em Programação Geométrica (PG). Para dimensionar as portas lógicas de um circuito, primeiramente elas são modeladas usando o modelo de chaves RC e o atraso é calculado usando o modelo de Elmore, que produz funções posinomiais possibilitando a resolução do problema por programação geométrica. Para cada porta é utilizado um fator de escala que multiplica a largura dos seus transistores, onde as variáveis que representam os fatores de escala são as variáveis de otimização do problema. O dimensionador de portas desenvolvido neste trabalho é para circuitos CMOS e é parametrizável para diversas tecnologias de fabricação CMOS. Além disso, a otimização pode ser feita de duas maneiras, minimizando o atraso restringindo a área do circuito ou, minimizando a área e restringindo o atraso do circuito. Para testar o dimensionador de portas foram consideradas duas tecnologias de fabricação diferentes, 45nm e 350nm, onde os resultados foram comparados com o dimensionamento fornecido em uma típica biblioteca de células. Para a tecnologia de 45nm, o dimensionamento de portas minimizando o atraso, fornecido pelo método proposto neste trabalho, obteve uma redução, em média, de 21% no atraso, mantendo a mesma área e potência do dimensionamento fornecido pela biblioteca de standard cells. Após, fez-se uma otimização de área, ainda considerando a tecnologia de 45nm, onde o atraso é restrito ao valor encontrado na minimização de atraso. Essa otimização secundária resultou em uma redução média de 28,2% em área e 27,3% em potência, comparado aos valores dados pela minimização de atraso. Isso mostra que, ao fazer a minimização de atraso seguida da minimização de área, ou vice-versa, encontra-se o menor atraso e a menor área para o circuito, onde uma otimização não impede a outra. As mesmas otimizações foram feitas para a tecnologia de 350nm, onde o dimensionamento de portas considerando a minimização de atraso obteve uma redução, em média, de 4,5% no atraso, mantendo os valores de consumo de potência e área semelhantes aos valores dados pelo dimensionamento fornecido em uma biblioteca comercial de células em 350nm. A minimização de área, feita em seguida, restringindo o atraso ao valor dado pela minimização de atraso foi capaz de reduzir a área em 29,9%, em média, e a potência em 28,5%, em média. / In this work a gate sizing tool is developed using problem optimization techniques based on Geometric Programming. To size the gates in a circuit, first, the logic gates are modeled using the RC switch model and the delay is calculated using Elmore delay model, which produces posynomial functions, enabling the problem solution by geometric programming. For each port a scale factor is set that multiplies the transistors width, where the variables that represent the scale factors are the problem optimization variables. Gate sizing developed in this work is for CMOS circuits and is configurable to several CMOS manufacturing technologies. Moreover, the optimization can be done in two ways, minimizing delay restricting area or by minimizing area restricting circuit delay. In this work, gate sizing tests were made considers two different technologies, 45nm and 350nm, where the results were compared with the sizing available in a typical standard-cell library. For 45nm technology, the gate sizing proposed in this work considering delay minimization, obtained a reduction, in average, of 21% in delay, keeping the same area and power values of the sizing provided by standard-cells library. After, it was made an area optimization restricting delay to the value found at delay minimization. This optimization allowed an average reduction of 28.2% in area and 27.3% in power consumption, compared to the values obtained by delay minimization. This shows that by making the minimization of delay followed by the minimization of area, the smallest delay and the smallest area for the circuit is found, where an optimization does not prevent the other. The same optimizations were made for 350nm technology, where gate sizing considering delay minimization achieved a reduction, on average, of 4.5% in delay, keeping power consumption and area values similar to the values given using the sizes found in a commercial standard-cell library in 350nm. The area minimization, restricting delay to the value given by delay minimization, was able to reduce the area in 29.9% and power at 28.5%, on average.