In this study, a new gas turbine monitoring system being able to carry out appropriate run process is set up for a gas turbine with 250 kW power rating and its accessories. The system with the mechanical and electrical connections of the required sub-parts is transformed to a kind of the test stand. Performance test result calculation method is described. In addition that, performance evaluation software being able to apply with the completion of the preliminary performance tests is developed for this gas turbine. This system has infrastructure for the gas turbine sub-components performance and aerothermodynamics research. This system is also designed for aviation training facility as a training material for the gas turbine start and run demonstration. This system provides the preliminary gas turbine performance research requirements in the laboratory environment.

<p dir="ltr">The design of hardware platform in acoustic sensing is critical. The number and the spatial arrangement of microphones play a huge role in sensing performance. All microphones should be properly processed for simultaneous recording. This work introduces an FPGA-based acoustic transceiver system supporting acoustic sensing with custom acoustic signals. The system contains 16 microphones and a speaker synchronized during sensing processes. The microphones were arranged into an ‘L’ shape with eight microphones on each line for a better resolution of angle estimation on two dimensions. The microphones were placed on a specifically designed PCB to achieve an optimal distance of the half-wavelength of acoustic signals for optimized sensing performance. A microphone interface was implemented on Ultra96-V2 FPGA for handling the simultaneous high-speed data streams. The system features an implementation of full-level data transmission up to the top-level Python program. To evaluate the sensing performance of the system, we conducted an experiment used Frequency Modulated Continuous Wave (FMCW) as the transmitted acoustic signal. The result of evaluation shown the accurate sensing of range, velocity and relative angle of a moving hand on the two dimensions corresponding to the microphone groups.</p>

<p>The 2020 pandemic emphasized the need for accessible and accurate point-of-care diagnostic tests. With the continued development of isothermal nucleic acid amplification tests, this can be achieved. A requirement of these tests includes heating and holding a specific temperature, in this case, 65C for 30 minutes, for amplification to occur. To achieve this, heaters often require external feedback to control the temperature; bringing up the device’s cost. Several self-regulating heaters have been made with materials having a positive thermal coefficient of resistance eliminating the need for complex circuitry. With this property, point-of-care diagnostic tests can be simplified and made more accessible. In this study, ink-based positive thermal coefficient of resistance heaters are developed and characterized using the scalable method of screen printing to achieve 65C and aid in the detection of SARS-CoV-2. Various curing methods and screen-printing parameters were evaluated to improve the stability and understanding of the reproducibility of the heaters. The longevity of the heaters was evaluated with oxidation studies and a COMSOL model was created to study the heat transfer within the device. Furthermore, the heaters were successfully implemented into a second-generation electronic point-of-care diagnostic device. Detection of SARS-CoV-2 using a self-regulating heater removes the need for complex circuitry, improving the accessibility of point-of-care tests with the potential to be expanded to a wide range of pathogen detection. </p>

Memory system design is increasingly influencing modern multi-core architectures from both performance and power perspectives. Both main memory latency and bandwidth have im-proved at a rate that is slower than the increase in processor core count and speed. Off-chip memory, primarily built from DRAM, has received significant attention in terms of architecture and design for higher performance. These performance improvement techniques include sophisticated memory access scheduling, use of multiple memory controllers, mitigating the impact of DRAM refresh cycles, and so on. At the same time, new non-volatile memory technologies have become increasingly viable in terms of performance and energy. These alternative technologies offer different performance characteristics as compared to traditional DRAM. With the advent of 3D stacking, on-chip memory in the form of 3D stacked DRAM has opened up avenues for addressing the bandwidth and latency limitations of off-chip memory. Stacked DRAM is expected to offer abundant capacity — 100s of MBs to a few GBs — at higher bandwidth and lower latency. Researchers have proposed to use this capacity as an extension to main memory, or as a large last-level DRAM cache. When leveraged as a cache, stacked DRAM provides opportunities and challenges for improving cache hit rate, access latency, and off-chip bandwidth. Thus, designing off-chip and on-chip memory systems for multi-core architectures is complex, compounded by the myriad architectural, design and technological choices, combined with the characteristics of application workloads. Applications have inherent spatial local-ity and access parallelism that influence the memory system response in terms of latency and bandwidth. In this thesis, we construct an analytical model of the off-chip main memory system to comprehend this diverse space and to study the impact of memory system parameters and work-load characteristics from latency and bandwidth perspectives. Our model, called ANATOMY, uses a queuing network formulation of the memory system parameterized with workload characteristics to obtain a closed form solution for the average miss penalty experienced by the last-level cache. We validate the model across a wide variety of memory configurations on four-core, eight-core and sixteen-core architectures. ANATOMY is able to predict memory latency with average errors of 8.1%, 4.1%and 9.7%over quad-core, eight-core and sixteen-core configurations respectively. Further, ANATOMY identifie better performing design points accurately thereby allowing architects and designers to explore the more promising design points in greater detail. We demonstrate the extensibility and applicability of our model by exploring a variety of memory design choices such as the impact of clock speed, benefit of multiple memory controllers, the role of banks and channel width, and so on. We also demonstrate ANATOMY’s ability to capture architectural elements such as memory scheduling mechanisms and impact of DRAM refresh cycles. In all of these studies, ANATOMY provides insight into sources of memory performance bottlenecks and is able to quantitatively predict the benefit of redressing them. An insight from the model suggests that the provisioning of multiple small row-buffers in each DRAM bank achieves better performance than the traditional one (large) row-buffer per bank design. Multiple row-buffers also enable newer performance improvement opportunities such as intra-bank parallelism between data transfers and row activations, and smart row-buffer allocation schemes based on workload demand. Our evaluation (both using the analytical model and detailed cycle-accurate simulation) shows that the proposed DRAM re-organization achieves significant speed-up as well as energy reduction. Next we examine the role of on-chip stacked DRAM caches at improving performance by reducing the load on off-chip main memory. We extend ANATOMY to cover DRAM caches. ANATOMY-Cache takes into account all the key parameters/design issues governing DRAM cache organization namely, where the cache metadata is stored and accessed, the role of cache block size and set associativity and the impact of block size on row-buffer hit rate and off-chip bandwidth. Yet the model is kept simple and provides a closed form solution for the aver-age miss penalty experienced by the last-level SRAM cache. ANATOMY-Cache is validated against detailed architecture simulations and shown to have latency estimation errors of 10.7% and 8.8%on average in quad-core and eight-core configurations respectively. An interesting in-sight from the model suggests that under high load, it is better to bypass the congested DRAM cache and leverage the available idle main memory bandwidth. We use this insight to propose a refresh reduction mechanism that virtually eliminates refresh overhead in DRAM caches. We implement a low-overhead hardware mechanism to record accesses to recent DRAM cache pages and refresh only these pages. Older cache pages are considered invalid and serviced from the (idle) main memory. This technique achieves average refresh reduction of 90% with resulting memory energy savings of 9%and overall performance improvement of 3.7%. Finally, we propose a new DRAM cache organization that achieves higher cache hit rate, lower latency and lower off-chip bandwidth demand. Called the Bi-Modal Cache, our cache organization brings three independent improvements together: (i) it enables parallel tag and data accesses, (ii) it eliminates a large fraction of tag accesses entirely by use of a novel way locator and (iii) it improves cache space utilization by organizing the cache sets as a combination of some big blocks (512B) and some small blocks (64B). The Bi-Modal Cache reduces hit latency by use of the way locator and parallel tag and data accesses. It improves hit rate by leveraging the cache capacity efficiently – blocks with low spatial reuse are allocated in the cache at 64B granularity thereby reducing both wasted off-chip bandwidth as well as cache internal fragmentation. Increased cache hit rate leads to reduction in off-chip bandwidth demand. Through detailed simulations, we demonstrate that the Bi-Modal Cache achieves overall performance improvement of 10.8%, 13.8% and 14.0% in quad-core, eight-core and sixteen-core workloads respectively over an aggressive baseline.

<p>  </p> <p>Cold chain logistics comprise a large portion of transported pharmaceutical medications and raw materials which must be preserved at specified temperatures to maintain consumer safety and efficacy. An immutable record of temperatures of transported pharmaceutical goods allows for mitigation of temperature-related issues of such drugs and their raw components. The recording of this information on a blockchain creates such an immutable record of this information which can be readily accessed by any relevant party. This can allow for any components which have not been kept at the appropriate temperatures to be removed from production. These data can also be used as inputs for smart contracts or for data analytic purposes. </p> <p>A theoretical framework for such a system, referred to as “TempEnsure” is described, which provides digital capture of the internal temperature of temperature-controlled shipping containers. The data are recorded in a blockchain system. Real world testing of this system was not possible due to monetary constraints, but the functional elements of the system, as well as potential improvements for the system, are discussed.</p>

<p dir="ltr">Achieving higher throughput is one of the most important requirements of a modern microcontroller. It is therefore not affordable for it to waste a considerable number of clock cycles in branch mispredictions. This paper proposes a hardware mechanism that makes microcontrollers forgo branch predictors, thereby removing branch mispredictions. The scope of this work is limited to low cost microcontroller cores that are applied in embedded systems. The proposed technique is implemented as five different modules which work together to forward required operands, resolve branches without prediction, and calculate the next instruction's address in the first stage of an in-order five stage pipelined micro-architecture. Since the address of successive instruction to a control transfer instruction is calculated in the first stage of pipeline, branch prediction is no longer necessary, thereby eliminating the clock cycle penalties occurred when using a branch predictor. The designed architecture was able to successfully calculate the address of next correct instruction and fetch it without any wastage of clock cycles except in cases where control transfer instructions are in true dependence with their immediate previous instructions. Further, we synthesized the proposed design with 7nm FinFET process and compared its latency with other designs to make sure that the microcontroller's operating frequency is not degraded by using this design. The critical path latency of instruction fetch stage integrated with the proposed architecture is 307 ps excluding the instruction cache access time.</p>

<p>Multifunctional additive manufacturing has the immense potential of addressing present needs within structural health monitoring by enabling a new additive manufacturing paradigm that redefines what a sensor is, or what sensors should resemble. To achieve this, the properties of printed components must be precisely tailored to meet structure specific and application specific requirements. However due to the limited number of commercially available multifunctional filaments, this research investigates the in-house creation of adaptable piezoresistive multifunctional filaments and their potential within structural health monitoring applications based upon their characterized piezoresistive responses. To do so, a rigid polylactic acid based-filament and a flexible thermoplastic polyurethane based-filament were modified to impart piezoresistive properties using carbon nanofibers. The filaments were produced using different mixing techniques, nanoparticle concentrations, and optimally selected manufacturing parameters from a design of experiments approach. The resulting filaments exhibited consistent resistivity values which were found to be less variable under specific mixing techniques than commercially available multifunctional filaments. This improved consistency was found to be a key factor which held back currently available piezoresistive filaments from fulfilling needs within structural health monitoring. To demonstrate the ability to meet these needs, the piezoresistive responses of three dog-bone shaped sensor sizes were measured under monotonic and cyclic loading conditions for the optimally manufactured filaments. The characterized piezoresistive responses demonstrated high strain sensitivities under both tensile and compressive loads. These piezoresistive sensors demonstrated the greatest sensitivity in tension, where all three sensor sizes exhibited gauge factors over 30. Cyclic loading supported these results and further demonstrated the accuracy and reliability of the printed sensors within SHM applications.</p>

[pt] Spoken Dialogue Systems (SDS s) são sistemas baseados em computadores desenvolvidos para fornecerem informações e realizar tarefas utilizando o diálogo como forma de interação. Eles são capazes de reconhecimento de voz, interpretação, gerenciamento de diálogo e são capazes de ter uma voz como saída de dados, tentando reproduzir uma interação natural falada entre um usuário humano e um sistema. SDS s provém diferentes serviços, todos através de linguagem falada com um sistema. Mesmo com todo o desenvolvimento nesta área, há escassez de informações sobre como avaliar a qualidade de tais sistemas com o propósito de otimização do mesmo. Com dois destes sistemas, BoRIS e INSPIRE, usados para reservas de restaurantes e gerenciamento de casas inteligentes, diversos experimentos foram conduzidos no passado, onde tais sistemas foram utilizados para resolver tarefas específicas. Os participantes avaliaram a qualidade do sistema em uma série de questões. Além disso, todas as interações foram gravadas e anotadas por um especialista.O desenvolvimento de métodos para avaliação de performance é um tópico aberto de pesquisa na área de SDS s. Seguindo a idéia do modelo PARADISE (PARAdigm for DIalogue System Evaluation – desenvolvido pro Walker e colaboradores na AT&T em 1998), diversos experimentos foram conduzidos para desenvolver modelos de previsão de performance de sistemas de reconhecimento de voz e linguagem falada. O objetivo desta dissertação de mestrado é desenvolver modelos que permitam a previsão de dimensões de qualidade percebidas por um usuário humano, baseado em parâmetros instrumentalmente mensuráveis utilizando dados coletados nos experimentos realizados com os sistemas BoRIS e INSPIRE , dois sistemas de reconhecimento de voz (o primeiro para busca de restaurantes e o segundo para Smart Homes). Diferentes algoritmos serão utilizados para análise (Regressão linear, Árvores de Regressão, Árvores de Classificação e Redes Neurais) e para cada um dos algoritmos, uma ferramenta diferente será programada em MATLAB, para poder servir de base para análise de experimentos futuros, sendo facilmente modificado para sistemas e parâmetros novos em estudos subsequentes.A idéia principal é desenvolver ferramentas que possam ajudar na otimização de um SDS sem o envolvimento direto de um usuário humano ou servir de ferramenta para estudos futuros na área. / [en] Spoken Dialogue Systems (SDS s) are computer-based systems developed to provide information and carry out tasks using speech as the interaction mode. They are capable of speech recognition, interpretation, management of dialogue and have speech output capabilities, trying to reproduce a more or less natural spoken interaction between a human user and the system. SDS s provide several different services, all through spoken language. Even with all this development, there is scarcity of information on ways to assess and evaluate the quality of such systems with the purpose of optimization. With two of these SDS s ,BoRIS and INSPIRE, (used for Restaurant Booking Services and Smart Home Systems), extensive experiments were conducted in the past, where the systems were used to resolve specific tasks. The evaluators rated the quality of the system on a multitude of scales. In addition to that, the interactions were recorded and annotated by an expert. The development of methods for performance evaluation is an open research issue in this area of SDS s. Following the idea of the PARADISE model (PARAdigm for DIalogue System Evaluation model, the most well-known model for this purpose (developed by Walker and co-workers at AT&T in 1998), several experiments were conducted to develop predictive models of spoken dialogue performance. The objective of this dissertation is to develop and assess models which allow the prediction of quality dimensions as perceived by the human user, based on instrumentally measurable variables using all the collected data from the BoRIS and INSPIRE systems. Different types of algorithms will be compared to their prediction performance and to how generic they are. Four different approaches will be used for these analyses: Linear regression, Regression Trees, Classification Trees and Neural Networks. For each of these methods, a different tool will be programmed using MATLAB, that can carry out all experiments from this work and be easily modified for new experiments with data from new systems or new variables on future studies. All the used MATLAB programs will be made available on the attached CD with an operation manual for future users as well as a guide to modify the existing programs to work on new data. The main idea is to develop tools that would help on the optimization of a spoken dialogue system without a direct involvement of the human user or serve as tools for future studies in this area.

<p>Convolutional neural networks (CNNs) have become important workloads due to their<br> impressive accuracy in tasks like image classification and recognition. Convolution operations<br> are compute intensive, and this cost profoundly increases with newer and better CNN models.<br> However, convolutions come with characteristics such as sparsity which can be exploited. In<br> this dissertation, we propose three different works to capture sparsity for faster performance<br> and reduced energy. </p> <p><br></p> <p>The first work is an accelerator design called <em>SparTen</em> for improving two-<br> sided sparsity (i.e, sparsity in both filters and feature maps) convolutions with fine-grained<br> sparsity. <em>SparTen</em> identifies efficient inner join as the key primitive for hardware acceleration<br> of sparse convolution. In addition, <em>SparTen</em> proposes load balancing schemes for higher<br> compute unit utilization. <em>SparTen</em> performs 4.7x, 1.8x and 3x better than dense architecture,<br> one-sided architecture and SCNN, the previous state of the art accelerator. The second work<br> <em>BARISTA</em> scales up SparTen (and SparTen like proposals) to large-scale implementation<br> with as many compute units as recent dense accelerators (e.g., Googles Tensor processing<br> unit) to achieve full speedups afforded by sparsity. However at such large scales, buffering,<br> on-chip bandwidth, and compute utilization are highly intertwined where optimizing for<br> one factor strains another and may invalidate some optimizations proposed in small-scale<br> implementations. <em>BARISTA</em> proposes novel techniques to balance the three factors in large-<br> scale accelerators. <em>BARISTA</em> performs 5.4x, 2.2x, 1.7x and 2.5x better than dense, one-<br> sided, naively scaled two-sided and an iso-area two-sided architecture, respectively. The last<br> work, <em>EUREKA</em> builds an efficient tensor core to execute dense, structured and unstructured<br> sparsity with losing efficiency. <em>EUREKA</em> achieves this by proposing novel techniques to<br> improve compute utilization by slightly tweaking operand stationarity. <em>EUREKA</em> achieves a<br> speedup of 5x, 2.5x, along with 3.2x and 1.7x energy reductions over Dense and structured<br> sparse execution respectively. <em>EUREKA</em> only incurs area and power overheads of 6% and<br> 11.5%, respectively, over Ampere</p>

<p dir="ltr">Powder Sprays such as Direct Energy Deposition and Cold Spray are rapidly growing and promising manufacturing methods in the Additive Manufacturing field, as they allow easy and localized delivery of powder to be fused to a substrate and consecutive layers. The relatively small size of nozzles allows for these methods to be mounted on CNC machines and Robotic Arms for the creation of complex shapes. However, these manufacturing methods are inherently stochastic, and therefore differences in powder size, shape, trajectory, and velocity can drastically affect whether they will deposit on a substrate. This variation results in an inherent reduction of deposition efficiency, leading to waste and the need for powder collection or recycling systems. The design of the nozzles can drastically affect the variation of powder trajectory and velocity on a holistic level, and thus understanding the gas-powder flow of these nozzles in respect to the features of said nozzles is crucial. This paper proposes and examines how changes in the nozzle geometry affect gas-powder flow and powder focusing for Direct Energy Deposition and Cold Spray. In addition, a new Pulsed Cold Spray nozzle design is proposed that will control the amount of gas and powder used by the nozzle via solenoid actuation. By making these changes to the nozzle, it is possible to improve deposition efficiency and reduce powder/gas waste in these processes, while also allowing for improved coating density. Furthermore, the research done in this thesis will also focus on novel applications to powder spray manufacturing methods, focusing on polymer metallization and part identification.</p>