As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC) implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC) architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. The processing elements (PEs) communicate with each other by exchanging messages over the network and these messages go through buffers in each router. Buffers are one of the major resource used by the routers in virtual channel flow control. In this thesis, we analyze two kinds of buffer allocation approaches, static and dynamic buffer allocations. These approaches aim to increase throughput and minimize latency by means of virtual channel flow control. In statically allocated buffer architecture, size and organization are design time decisions and thus, do not perform optimally for all traffic conditions. In addition, statically allocated virtual channel consumes a waste of area and significant leakage power. However, dynamic buffer allocation scheme claims that buffer utilization can be increased using dynamic virtual channels. Dynamic virtual channel regulator (ViChaR), have been proposed to use centralized buffer architecture which dynamically allocates virtual channels and buffer slots in real-time depending on traffic conditions. This ViChaR’s dynamic buffer management scheme increases buffer utilization, but it also increases design complexity. In this research, we reexamine performance, power consumption, and area of ViChaR’s buffer architecture through implementation. We implement a generic router and a ViChaR architecture using Verilog-HDL. These RTL codes are verified by dynamic simulation, and synthesized by Design Compiler to get area and power consumption. In addition, we get latency through Static Timing Analysis. The results show that a ViChaR’s dynamic buffer management scheme increases the latency and power consumption significantly even though it could increase buffer utilization. Therefore, we need a novel design to achieve high buffer utilization without a loss.

Recent advances in microfluidic technologies have enabled integration of the functional units for biological and chemical analysis onto miniaturized chips, called Labon- a-Chip (LOC). However, the effective manipulation and control of colloidal particles suspended in fluids are still challenging tasks due to the lack of clear characterization of particle control mechanisms. The aim of this dissertation is to develop microfluidic techniques and devices for manipulating colloids and biological particles with the utilization of alternating current (AC) electric fields and acoustic waves. The dissertation presents a simple theoretical tool for predicting the motion of colloidal particles in the presence of AC electric field. Dominant electrokinetic forces are explained as a function of the electric field conditions and material properties, and parametric experimental validations of the model are conducted with particles and biological species. Using the theoretical tool as an effective framework for designing electrokinetic systems, a dielectrophoresis (DEP) based microfluidic device for trapping bacterial spores from high conductivity media is developed. With a simple planar electrode having well defined electric field minima that can act as the targetattachment/ detection sites for integration of biosensors, negative DEP trapping of spores on patterned surfaces is successfully demonstrated. A further investigation of DEP colloidal manipulation under the effects of electrothermal flow induced by Joule heating of the applied electric field is conducted. A periodic structure of the electrothermal flow that enhances DEP trapping is numerically simulated and experimentally validated. An acoustic method is investigated for continuous sample concentration in a microscale device. Fast formation of particle streams focused at the pressure nodes is demonstrated by using the long-range forces of the ultrasonic standing waves (USW). High frequency actuation suitable for miniaturization of devices is successfully applied and the device performance and key parameters are explained. Further extension and integration of the technologies presented in this dissertation will enable a chip scale platform for various chemical and biological applications such as drug delivery, chemical analyses, point-of-care clinical diagnosis, biowarfare and biochemical agent detection/screening, and water quality control.

The demand for high performance microelectronic products drives the development of 3-D chip-stacking structure. By the introduction of through-silicon-via (TSV) into 3-D flip-chip packages, microelectronic performance is improved by increasing circuit capacity and diminishing signal delay. However, TSV-embedded structure also raises concerns over many reliability issues that come with the steep thermal and mechanical transient responses, increasing numbers of bi-material interfaces and reduced component sizes. In this research, defect initiation induced by thermalmechanical phenomena is studied to establish the early failure modes within 3-D flip-chip packages. It is found that low amplitude but extremely high frequency thermal stress waves would occur and attenuate rapidly in the first hundreds of nanoseconds upon power-on. Although the amplitude of these waves is far below material yielding points, their intrinsic characteristics of high frequency and high power density are capable of compromising the integrity of all flip-chip components. By conducting spectral analysis of the stress waves and applying the methodology of accumulated damage evaluation, it is demonstrated that micron crack initiation and interconnect debond are highly probable in the immediate proximity of the heat source. Such a negative impact exerted by the stress wave in the early, while brief, transient period is recognized as the short time scale dynamic effect. Researched results strongly indicate that short-time scale effects would inflict very serious reliability issues in 3-D flip-chip packages. The fact that 3-D flip-chip packages accommodate a large amount of reduced-size interconnects makes it vulnerable to the attack of short time scale propagating stress waves. In addition, the stacking structure also renders shearing effect extremely detrimental to 3-D flip-chip integrity. Finally, several guidelines effective in discouraging short-time scale effects and thus improving TSV flip-chip package reliability are proposed

Majority of the modern day compute intensive applications are heterogeneous in nature. To support their ever increasing computational requirements, present day System-on-Chip (SoC) architectures have adapted multicore style of modeling, thereby incorporating multiple, heterogeneous processing cores on a single chip. The emerging Network-On-Chip (NoC) interconnect paradigm provides a scalable and power-efficient solution for communication among multiple cores, serving as a powerful replacement for traditional bus based architectures. A fast, robust and exible emulation platform is the key to successful realization and validation of such architectures within a very short span of time. This research focuses on various aspects of Hardware/Software (HW/SW) codesign for AcENoCs (Accelerated Emulation Platform for NoCs), a Field Programmable Gate Array (FPGA) accelerated, con gurable, cycle accurate platform for emulation and validation of NoC architectures. This work also details the design, implementation and evaluation of AcENoCs' software framework along with the various design optimizations carried out and tradeoffs considered in AcENoCs' HW/SW codesign for achieving an optimum balance between emulated network dimensions and emulation performance. AcENoCs emulation platform is realized on a Xilinx Virtex-5 FPGA. AcENoCs' hardware framework consists of the NoC built using configurable hardware library components, while the software framework consists of Traffic Generators (TGs) and their associated source queues, Traffic Receptors (TRs) along with statistics analysis module and dynamically controlled emulation clock generator. The software framework is implemented using on-chip Xilinx MicroBlaze processor. This report also describes the interaction between various HW/SW events in an emulation cycle and assesses AcENoCs' performance speedup and tradeoffs over existing FPGA emulators and software simulators. FPGA synthesis results showed that networks with dimensions upto 5x5 could be accommodated inside the device. Varying synthetic traffic workloads, generated by TGs, were used to evaluate the network. Real application based traces were also run on AcENoCs platform to evaluate the performance improvement achieved in comparison to software simulators. For improving the emulator performance, software profiling was carried out to identify and optimize the software components consuming highest number of processor cycles in an emulation cycle. Emulation testcases were run and latency values recorded for varying traffic patterns in order to evaluate AcENoCs platform. Experimental results showed emulation speedups in order of 10000-12000X over HDL (Hardware Description Language) simulators and 14-47X over software simulators, without sacri cing cycle accuracy.

As the trend of miniaturization of complex integrated circuit(IC) devices, the current density of flip-chip solder bumps have increased significantly and each solder joint is supporting a current density close to or even over 104 A/cm2 .Therefore, in SnPb eutectic solder, which has a high diffusivity at the operating temperature due to its low melting point, the electromigration becomes a major reliability threat. Thus, the thesis is aimed to investigate the effects of electromigration behavior on flip-chip package eutectic Sn-Pb solder bumps reliability under high current density. The current densities are 2x104 A/cm2 and 1.5x104 A/cm2,the surface of die temperatures are 115¢Jand 95¢J.The bump temperature, the histories of the bump resistance, and mean time to failure (MTTF) testings were conducted. The failure mechanism was observed through SEM and EDS. From the results of the experiment, the dominant failure mode of the bump is due to electromigration behavior that causes voids at UBM/bump interface (cathode) when the sample¡¦s failure time is shorter. As the failure time is longer, the failure is also resulted from heat effect in addition to electromigration behavior.

For several decades of years, the electrical stimulation has been applied on rehabilitation of motional recovery for quadriplegic and paraplegic patients such as walking, standing, and cycling exercise. As the advancement of VLSI (very large scale integration) technology, the implantable micro-stimulators become feasible in recent years. This thesis presents an implantable system including an inductively coupling transceiver of power & data, a protocol of communication, and the implementation of a FES (Functional Electrical Stimulation ) SOC (System-On-chip). The first part of this thesis discusses the architecture of the proposed implantable FES system, including the theory of wireless power transmission, the implementation of mixed-signal circuits, the RS232 protocol, and two encoding methods of Manchester code and NRZ code. The second part of this thesis is focused on the multi-frequency stimulation of the implantable FES system, which comprises an advanced communication protocol suitable for multi-frequency stimulation function and a novel arrangement of interconnections for the chip.

Abstract Accompany a rapid growth in the semiconductor industry in the past few year, most components gradually used the small dimension as its basic structures. Due to the reduction of component size will induces highly concentrated on circuit and dimension, it also incurs a lots problem, such as electromagnetic interference, high temperature and thermal stress, which will decrease the product reliability. The most common damage in the semiconductor product is thermal fatigue, which is caused by thermal stress concentrated under repeatedly temperature variation loading. Usually, the thermal cycle loading is applied to induce the fatigue destruction and predict the product reliability, but this method spends one cycle for 80min which is time-consumption. Therefore, in this thesis, the finite element method package is used to simulate and evaluate the plastic variation of solder bump and the relation between different temperatures loading and equivalent plastic strain under different temperature range test. Through the Coffin-Manson equation, the equivalent plastic strain can be used to predict the fatigue live, which can be precisely accelerating the fatigue test.

Abstract A new technique for bonding of polymer micro-fluidic devices has been developed. This method can easily bond biochips with complex flow patterns and metal layer. Above all, using a patterned glass, the micro-channel structures on Poly-Methyl Meth-Acrylate (PMMA) substrates were generated by one-step hot embossing procedure. In contrast with the traditional thermal bonding, this paper presents low-temperature and low-pressure packaging for polymer micro-fluidic platforms. Furthermore, the disposable plastic biochip has successfully been tested by the measurement of tensile strength and surface roughness. This paper also reports details of the passive and active micro-mixers. According to experimental and numerical investigations, the mixing performance of passive micro-mixers is expectably to be found. In addition, to quantify the mixing concentration distribution in the micro-channel, it has been demonstrated by launching the image analysis programs. The bonding efficiency of the solvent is twenty four times as strong as thermal bonding efficiency.

High population density and the presence of many more motorcycles than cars make the noise environment in Taiwan different from that in other countries. There is growing concern about the electromagnetic effects within this environment. The electromagnetic environment is unique and the information about radio noise is not sufficient at this time. The interference of wireless communication system may be caused by the noise environment. Thus, we need to consider the influence that the noise causes. With the measured radio noise, the minimum suggested receive power in an urban environment ranges from 354 MHz to 426 MHz. It is analyzed by the means of Cumulative Distribution Function (CDF), Amplitude Probability Distribution (APD), Noise Amplitude Distribution (NAD), Pulse Duration Distribution (PDD), Pulse Spacing Distribution (PSD) and Average Crossing Rate (ACR). We measured the properties of noise at an urban center, a nearby port, and a freeway exit, which are located in the same city, and on a hill lying adjacent to the city. We chose an urban center and a nearby hill as the noise environment for the following reasons: (a) The noise margin at urban areas is smaller than that at suburban and rural areas. (b) The coverage of the measurement on a hill is larger than that in a city. (c) The relation of the noise environment between a hill and an urban center can be obtained. The statistical distributions of the four particular noise environments are shown and design constraints for a broadcasting system are revealed. Secondly, we also provide a technology for designing miniature Rogowski coils on glass substrates to obtain current sensors for high operating frequencies in this thesis. The coils are useful for measurement of a small current on a microstrip line at high frequencies. In our experiments, a 50 Ohm microstrip line is driven by an input voltage of 100 mV. A frequency as high as 6 GHz has been used. The highest frequency is limited by the oscilloscope available to us. Geometric effects of the device were investigated to obtain the sufficient output voltage at high frequencies. The induced output voltage can approach approximately 7 mV by modifying the structure of Rogowski coils. At the same time, On-chip solenoid inductors for high frequency magnetic integrated circuits are proposed. The eddy current loss was reduced by dividing the inductor into three consecutive inductors connected in series. The inductor has an inductance of 1.1 nH and the maximum quality factor (Qmax) of 50.5. The self-resonant frequency and the operating frequency at Qmax are greater than 17.5 GHz and 16.7 GHz, respectively.

The trend of electrical products is light, thin and minimized with the fast operation and multi functionality, which also drives assembly technology towards the same goal. In advanced assembly technology, flip-chip is the one that can achieve the purposes. The pitch and size of a bump, which is in charge of current transmit, are also getting small. The prohibition of using lead content material also stimulates the development of lead-free material in the related industries. The paper is focused on adopting lead free solder paste such as Sn/Ag1.0/Cu0.5 and Sn/Ag4.0/Cu0.5, together with Al/NiV/Cu UBM made by bumping technology. The empirical analysis is based the shear strength of three different bump heights. The result shows the higher the content of Ag, the higher of the initial shear strength. Moreover, the experiment also investigated two solder bump IMC conditions and shear strength by using multi-reflow. The result shows that the IMC of Sn/Ag4.0/Cu0.5 solder paste increases after times of multi-reflow, but the shear strength was sharply decreased. The reliability test was also performed, such as temperature cycling test, temperature and humidity test, highly accelerated temperature and humidity stress test, high temperature storage life test. It¡¦s found the Sn/Ag1.0/Cu0.5 solder bump could maintain the original ductility; while the Sn/Ag4.0/Cu0.5 solder bump was decreasing the ductility due to the generation of IMC. Keyword¡GShear Strength, Flip-chip, Bump, IMC