This thesis presents techniques to implement analog-to-digital converters (ADCs) under an ultra-low-supply-voltage of 0.2 V to reduce the power consumption. The thesis proposes a dynamic bulk biasing circuit to adjust the PMOS bulk voltage to balance the NMOS and PMOS drain currents to guarantee functionality in the presence of process, voltage, and temperature variations. The dynamic bulk bias circuit is analyzed rigorously to show its functionality. This thesis also describes a new comparator suitable for a 0.2-V supply using ac-coupling, stacked input pairs, and voltage-boosted load capacitor. A 10-bit 5-kS/s successive-approximation-register (SAR) ADC in a 180-nm CMOS process with a supply voltage of 0.2 V demonstrates these ideas. The ADC exhibits a differential nonlinearity (DNL) and integral nonlinearity (INL) within +0.42/-0.45 and +0.62/-0.67 LSB, respectively. The measured SFDR and SNDR at 5 kS/s with a Nyquist-frequency input are 65.9 dB and 52.1 dB, respectively. The entire ADC and dynamic bulk biasing circuitry consume 22 nW including leakage power to yield a figure-of-meirt (FoM) of 8.8 fJ/conv.-step. Measurements of multiple chips show the proposed dynamic bulk biasing fully recovers the ADC performance when the supply voltage is varied. The nW power consumption makes the design well suited for wireless sensor node and energy harvester applications.

京都大学 / 0048 / 新制・課程博士 / 博士(医学) / 甲第20224号 / 医博第4183号 / 新制||医||1019(附属図書館) / 京都大学大学院医学研究科医学専攻 / (主査)教授 増永 慎一郎, 教授 武藤 学, 教授 羽賀 博典 / 学位規則第4条第1項該当 / Doctor of Medical Science / Kyoto University / DFAM

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Analog-to-digital converters (ADCs) are used to convert analog signals to the digital domain in digital communications systems. An ADC used in wireless communications should meet the necessary requirements for the worst-case channel condition. However, the worst-case scenario rarely occurs. As a consequence, a high-resolution and subsequently high power ADC designed for the worst case is not required for most operating conditions. A solution to reduce the power dissipation of ADCs in wireless digital communications systems is to detect the current channel condition and to dynamically vary the resolution of the ADC according to the given channel condition. In this thesis, we investigated an ADC that can change its resolution dynamically and, consequently, its power dissipation. Our ADC is a switched-current, redundant signed-digit (RSD) cyclic implementation that easily incorporates variable resolution. Furthermore, the RSD cyclic algorithm is insensitive to offsets, allowing simple, low-power comparators. Our ADC is implemented in a 0.35 um CMOS technology with a single-ended 3.3 V power supply. Our ADC has a maximum power dissipation of 6.35 mW for a 12-bit resolution and dissipates an average of 10 percent less power when the resolution is decreased by two bits. Simulation results indicate our ADC achieves a bit rate of 1.7 MHz and has a SNR of 84 dB for the maximum input frequency of 8.3 kHz. / Master of Science