<p>The introduction of the digital image sensor has triggered a revolution in the field of imaging. It has not only just replaced the conventional silver halide film based imaging system, but has also enormously widened the scope of imaging applications. Previously, charge-coupled devices (CCDs) were the most popular technology for image sensors. But in the past decade, they have been rapidly replaced by the CMOS image sensor (CIS) technology. The CCD image sensors offers higher sensitivity, wider dynamic range and better resolution compared to its CMOS imager counterparts. However, the lower power performance, higher speed of operation, easier integration with signal control and processing circuitries, and the use well-established mainstream fabrication process of CMOS technology, are key advantages that have served to propel CMOS imagers beyond CCDs in the market.</p> <p>However, CIS suffers from higher temporal noise compared to that of CCDs. One of the major noise sources in CIS is the 1/ noise generated from the in-pixel active amplifier. Due to continuous shrinking of MOS devices, the random telegraph signal (RTS) noise is emerging as a dominant noise source over other low frequency noise in CMOS imagers, resulting into reduced imaging performance.</p> <p>The RTS noise which evolves from trapping and de-trapping of electrons by the defects in the oxide, causes fluctuation in the drain current of the MOSFET. In this work, we have carried out time-domain measurement of RTS noise in CIS pixels. The time domain RTS measurements provide useful information about its characteristics in different operating conditions, which can be further used to extract the trap parameters and determine the optimum settings of operation of CIS.</p> <p>The capability of integrating various on-chip operations, higher speed and lower fabrication cost has made the CIS a good choice for various imaging applications. In order to demonstrate the extent of possible applications of CIS, we have developed an imaging system using a CIS. Two major concerns of biomedical imaging systems are their speed and cost. The system presented here is implemented using a CIS and FPGA (field programmable gate array) that provides a low-cost and high frame rate solution for biomedical microscopy.</p> / Master of Applied Science (MASc)

This work extends the technology of amorphous silicon (a-Si) thin film transistors (TFTs) from traditional switching applications to on-pixel signal amplification for large area digital imaging and in particular, is aimed towards enabling emerging low noise, high resolution and high frame rate medical diagnostic imaging modalities such as digital tomosynthesis. A two transistor (2T) pixel amplifier circuit based on a novel charge-gate thin film transistor (TFT) device architecture is introduced to shrink the TFT based pixel readout circuit size and complexity and thus, improve the imaging array resolution and reliability of the TFT fabrication process. The high resolution pixel amplifier results in improved electrical performance such as on-pixel amplification gain, input referred noise and faster readouts. In this research, a charge-gated TFT that operates as both a switched amplifier and driver is used to replace two transistors (the addressing switch and the amplifier transistor) of previously reported three transistor (3T) APS pixel circuits.. In addition to enabling smaller pixels, the proposed 2T pixel amplifier results in better signal-to-noise (SNR) by removing the large flicker noise source associated with the switched TFT and increased pixel transconductance gain since the large ON-state resistance of the switched TFT is removed from the source of the amplifier TFT. Alternate configurations of 2T APS architectures based on source or drain switched TFTs are also investigated, compared, and contrasted to the gate switched architecture using charge-gated TFT. A new driving scheme based on multiple row resetting is introduced which combined with the on-pixel gain of the APS, offers considerable improvements in imaging frame rates beyond those feasible for PPS based pixels. The novel developed 2T APS architectures is implemented in single pixel test structures and in 88 pixel test arrays with a pixel pitch of 100 µm. The devices were fabricated using an in-house developed top-gate TFT fabrication process. Measured characteristics of the test devices confirm the performance expectations of the 2T architecture design. Based on parameters extracted from fabricated TFTs, the input referred noise is calculated, and the instability in pixel transconductance gain over prolonged operation tine is projected for different imaging frame rates. 2T APS test arrays were packaged and integrated with an amorphous selenium (a-Se) direct x-ray detector, and the x-ray response of the a-Se detector integrated with the novel readout circuit was evaluated. The special features of the APS such as non-destructive readout and voltage programmable on-pixel gain control are verified. The research presented in this thesis extends amorphous silicon pixel amplifier technology into the area of high density pixel arrays such as large area medical X-ray imagers for digital mammography tomosynthesis. It underscores novel device and circuit design as an effective method of overcoming the inherent shortcomings of the a-Si material . Although the developed device and circuit ideas were implemented and tested using a-Si TFTs, the scope of the device and circuit designs is not limited to amorphous silicon technology and has the potential to be applied to more mainstream technologies, for example, in CMOS active pixel sensor (APS) based digital cameras.

This work extends the technology of amorphous silicon (a-Si) thin film transistors (TFTs) from traditional switching applications to on-pixel signal amplification for large area digital imaging and in particular, is aimed towards enabling emerging low noise, high resolution and high frame rate medical diagnostic imaging modalities such as digital tomosynthesis. A two transistor (2T) pixel amplifier circuit based on a novel charge-gate thin film transistor (TFT) device architecture is introduced to shrink the TFT based pixel readout circuit size and complexity and thus, improve the imaging array resolution and reliability of the TFT fabrication process. The high resolution pixel amplifier results in improved electrical performance such as on-pixel amplification gain, input referred noise and faster readouts. In this research, a charge-gated TFT that operates as both a switched amplifier and driver is used to replace two transistors (the addressing switch and the amplifier transistor) of previously reported three transistor (3T) APS pixel circuits.. In addition to enabling smaller pixels, the proposed 2T pixel amplifier results in better signal-to-noise (SNR) by removing the large flicker noise source associated with the switched TFT and increased pixel transconductance gain since the large ON-state resistance of the switched TFT is removed from the source of the amplifier TFT. Alternate configurations of 2T APS architectures based on source or drain switched TFTs are also investigated, compared, and contrasted to the gate switched architecture using charge-gated TFT. A new driving scheme based on multiple row resetting is introduced which combined with the on-pixel gain of the APS, offers considerable improvements in imaging frame rates beyond those feasible for PPS based pixels. The novel developed 2T APS architectures is implemented in single pixel test structures and in 88 pixel test arrays with a pixel pitch of 100 µm. The devices were fabricated using an in-house developed top-gate TFT fabrication process. Measured characteristics of the test devices confirm the performance expectations of the 2T architecture design. Based on parameters extracted from fabricated TFTs, the input referred noise is calculated, and the instability in pixel transconductance gain over prolonged operation tine is projected for different imaging frame rates. 2T APS test arrays were packaged and integrated with an amorphous selenium (a-Se) direct x-ray detector, and the x-ray response of the a-Se detector integrated with the novel readout circuit was evaluated. The special features of the APS such as non-destructive readout and voltage programmable on-pixel gain control are verified. The research presented in this thesis extends amorphous silicon pixel amplifier technology into the area of high density pixel arrays such as large area medical X-ray imagers for digital mammography tomosynthesis. It underscores novel device and circuit design as an effective method of overcoming the inherent shortcomings of the a-Si material . Although the developed device and circuit ideas were implemented and tested using a-Si TFTs, the scope of the device and circuit designs is not limited to amorphous silicon technology and has the potential to be applied to more mainstream technologies, for example, in CMOS active pixel sensor (APS) based digital cameras.

A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application. Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time. A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work v aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.

Monolithic Active Pixel Sensors (MAPS) are good candidates to be used in High Energy Physics (HEP) experiments for charged particle detection. In the HEP applications, MAPS chips are placed very close to the interaction point and are directly exposed to harsh environmental radiation. This thesis focuses on the study and improvement of the MAPS radiation hardness. The main radiation effects and the research progress of MAPS are studied firstly. During the study, the SRAM IP cores built in MAPS are found limiting the radiation hardness of the whole MAPS chips. Consequently, in order to improve the radiation hardness of MAPS, three radiation hard memories are designed and evaluated for the HEP experiments. In order to replace the SRAM IP cores, a radiation hard SRAM is developed on a very limited area. For smaller feature size processes, in which the single event upset (SEU) effects get significant, a radiation hard SRAM with enhanced SEU tolerance is implemented by an error detection and correction algorithm and a bit-interleaving storage. In order to obtain higher radiation tolerance and higher circuitry density, a dual-port memory with an original 2-transistor cell is developed and evaluated for future MAPS chips. Finally, the radiation hardness of the MAPS chips using new available processes is studied, and the future works are prospected.

A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application. Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time. A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work v aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.

Submitted by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2016-11-25T15:39:21Z No. of bitstreams: 1 Dissertação - Ewerton G. Oliveira.pdf: 6135162 bytes, checksum: 3a074865f59774e056e5a06dd0c49501 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2016-11-25T15:39:37Z (GMT) No. of bitstreams: 1 Dissertação - Ewerton G. Oliveira.pdf: 6135162 bytes, checksum: 3a074865f59774e056e5a06dd0c49501 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2016-11-25T15:39:56Z (GMT) No. of bitstreams: 1 Dissertação - Ewerton G. Oliveira.pdf: 6135162 bytes, checksum: 3a074865f59774e056e5a06dd0c49501 (MD5) / Made available in DSpace on 2016-11-25T15:39:56Z (GMT). No. of bitstreams: 1 Dissertação - Ewerton G. Oliveira.pdf: 6135162 bytes, checksum: 3a074865f59774e056e5a06dd0c49501 (MD5) Previous issue date: 2016-04-18 / This work presents a study on the behavior and effectiveness of different Fixed-Pattern Noise (FPN) reduction techniques applied to different pixel topologies operating in logarithmic mode. The purpose of such study is the establishment of a consistent way to perform fair cross comparison of the effectiveness of different FPN attenuation techniques applied to pixels with different topologies and designed in the same technological node, and thus establish judgment criteria for determining which topology will be most suitable for implementation of an image sensor operating in logarithimic mode. Investigations of the effectiveness of two similar FPN reduction techniques applied to four different pixel topologies were performed through Monte Carlo simulations. The analyses of results of output signal swing, total and residual FPN, signal-to-distortion ratio, power consumption and fill factor are able to demonstrate which pixel topologies yield better results in each of these criteria. Such results provide valuable data that allows a more concise decision on which pixel topology and FPN reduction technique to choose in the design of an imager array with wide dynamic range. / Este trabalho apresenta um estudo sobre o comportamento e eficácia de diferentes técnicas de redução de ruído de padrão fixo, do inglês fixed-pattern noise (FPN), aplicadas a diferentes topologias de pixel operando em modo logarítmico. A finalidade deste estudo é o estabelecimento de um meio consistente para realizar comparação cruzada imparcial da eficácia de diferentes técnicas de redução de FPN aplicadas a pixeis com diferentes topologias e projetados sob o mesmo rótulo tecnológico, e assim estabelecer critérios de julgamento que permitam determinar qual topologia será a mais adequada para implementação de um sensor de imagem operando em modo logarítmico. Investigações da eficácia de duas técnicas de redução de FPN similares aplicadas a quatro diferentes topologias de pixel foram realizadas através de simulações Monte Carlo. As análises dos resultados de excursão do sinal de saída, FPN total e residual, razão de distorção do sinal, consumo de energia e fator de preenchimento são capazes de demonstrar que topologias de pixel produzem melhores resultados em cada um destes critérios. Tais resultados proporcionam dados valiosos que permitem uma mais concisa decisão sobre qual topologia de pixel e técnica de redução de FPN escolher no projeto de um sensor de imagem com largo alcance dinâmico.

Quelles sont les particules élémentaires et comment l'univers proviennent sont les principales forces motrices de la physique des hautes énergies. Afin de démontrer le modèle standard et découvrez la nouvelle physique, plusieurs détecteurs sont construits pour les expériences en physique des hautes énergies. Capteurs à pixels CMOS offrent un compromis attirant entre la vitesse de lecture, le budget matériel, la tolérance au rayonnement, la consommation d'énergie et la granularité, par rapport aux capteurs à pixels hybrides et des dispositifs à transfert de charge. Ainsi, les CPS sont un bon choix pour détecter les particules chargées dans les détecteurs de vertex et des télescopes de faisceau. La distribution de puissance devient un enjeu important dans les détecteurs à venir, puisque une quantité considérable de capteurs seront installés. Malheureusement, le «Independent Powering» échoue, comme l'approche traditionnelle. Afin de résoudre les problèmes de distribution de puissance et de fournir des tensions silencieuses, cette thèse se concentre sur la conception de la gestion de l'alimentation à faible bruit, à basse consommation d'énergie, de petite taille et sur-puce pleinement pour les CPS. Les CPS sont d'abord introduits en tirer les exigences de conception de la gestion de l'alimentation. La distribution de puissance dédiées à les CPS est ensuite proposé, dans laquelle la gestion de l'alimentation est utilisée comme seconde étape de conversion de puissance. Deux régulateurs sur-puce pleinement sont proposés pour générer la tension d'alimentation analogique et de la tension d'alimentation de référence requis par l'opération d'échantillonnage double corrélé, respectivement. Deux prototypes ont vérifié ces régulateurs. Ils peuvent répondre aux exigences des CPS. En outre, les techniques de gestion de l'alimentation et de la conception tolérance au rayonnement sont également présentés dans cette thèse. / What are the elementary particles and how did the universe originate are the main driving forces in the high energy physics. In order to further demonstrate the standard model and discover new physics, several detectors are built for the high energy physics experiments. CMOS pixel sensors (CPS) can achieve an attractive tradeoff among many performance parameters, such as readout speed, granularity, material budget, power dissipation, radiation tolerance and integrating readout circuitry on the same substrate, compared with the hybrid pixel sensors and charge coupled devices. Thus, the CPS is a good candidate for tracking the charged particles in vertex detectors and beam telescopes.The power distribution becomes an important issue in the future detectors, since a considerable amount of sensors will be installed. Unfortunately, the independent powering has been proved to fail. In order to solve the power distribution challenges and to provide noiseless voltages, this thesis focuses on the design of a low noise, limited area, low power consumption and full on-chip power management in CPS chips. The CPS are firstly introduced drawing the design requirements of the power management. The power distribution dedicated to CPS chips is then proposed, in which the power management is utilized as the second power conversion stage. Two full on-chip regulators are proposed to generate the analog power supply voltage and the reference voltage required by correlated double sampling operation, respectively. Two prototypes have verified these regulators. They can meet the requirements of CPS. Moreover, the power management techniques and the radiation tolerance design are also presented in this thesis.

Cette thèse est une contribution au document intitulé "Detector Baseline Document (DBD)" décrivant le conceptde détecteur ILD envisagé auprès du collisionneur linéaire international électron-positon ILC (acronyme del'anglais International Linear Collider).Les objectifs de physique de l'ILD nécessitent un détecteur de vertex (VXD) particulièrement léger, rapide et trèsgranulaire permettant d'atteindre une résolution sans précédent sur le paramètre d'impact des trajectoiresreconstruites des particules produites dans les interactions étudiées. Le principal objectif de cette thèse est demontrer comment optimiser les paramètres du VXD dans le cas ou il est composé de Capteurs à Pixels Actifsfabriqués en technologie industrielle CMOS (CAPS). Ce travail a été réalisé en étudiant la sensibilité desperformances d'étiquetage des saveurs lourdes et de la précision sur les rapports d'embranchement hadroniquedu boson de Higgs aux différents paramètres du VXD.Le cahier des charges du VXD, particulièrement ambitieux, a nécessité le développement d'une nouvelletechnologie de capteurs de pixels de silicium, les CAPS, dont le groupe PICSEL de l'IPHC est à l'origine. Lavitesse de lecture et l'influence des paramètres qui régissent la fabrication des capteurs en fonderie ont étéétudiées dans cette thèse, et des prototypesde CAPS ont été caractérisés sur faisceau de particules. Enfin, les performances de trajectométrie d'un VXDcomposé de CAPS a été évalué avec des études de simulation. / This thesis is a contribution to the " Detector Baseline Document ", describing the ILD detector which is intendedfor the International Linear Collider (ILC).The physics goals of the ILD call for a vertex detector (VXD) particularly light, rapid and very granular allowing toreach an unprecedented resolution on the impact parameter of the tracks that reconstruct the particles producedin the studied interactions. The principle goal of this thesis is to show how to optimise the parameters of the VXDin the case that is composed of Active Pixel Sensors manufactured in industrial CMOS technology (CAPS). Thiswork has been realised by studying the sensitivity of the performance of the heavy flavour tagging and theprecision on the hadronic branching fractions of the Higgs boson as a function of different sets of VXDparameters.The specifications of the VXD, particularly ambitious, call for the development of a novel silicon pixel sensorstechnology, the CAPS, which was pioneered by the PICSEL group of IPHC. The readout speed and the influenceof the fabrication parameters have been studied in this thesis, and CAPS prototypes have been characterised intest beams. Finally, the tracking performance of a CAPS based VXD has been evaluated with simulation studies.

Les capteurs monolithiques actifs à pixels (Monolithic Active Pixel Sensors, MAPS) sont de bons candidats pour être utilisés dans des expériences en Physique des Hautes Énergies (PHE) pour la détection des particules chargées. Dans les applications en PHE, des puces MAPS sont placées dans le voisinage immédiat du point d’interaction et sont directement exposées au rayonnement intense de leur environnement. Dans cette thèse, nous avons étudié et amélioré la résistance aux radiations des MAPS. Les effets principaux de l’irradiation et le progrès de la recherche sur les MAPS sont étudiés tout d'abord. Nous avons constaté que les cœurs des SRAM IP incorporées dans la puce MAPS limitent sensiblement la tolérance aux radiations de la puce MAPS entière. Aussi, pour améliorer la radiorésistance des MAPS, trois mémoires radiorésistantes sont conçues et évaluées pour les expériences en PHE. Pour remplacer les cœurs des IP SRAM, une SRAM radiorésistante est développée sur une petite surface. Pour les procédés de plus petit taille de grille des transistors, dans lequel les effets SEU (Single Event Upset) deviennent significatifs, une SRAM radiorésistante avec une tolérance SEU accrue est réalisée à l’aide d’un algorithme de détection et de correction d'erreurs (Error Detection And Correction, EDAC) et un stockage entrelacé des bits. Afin d'obtenir une tolérance aux rayonnements et une densité de micro-circuits plus élevées, une mémoire à double accès avec une cellule à 2 transistors originale est développée et évaluée pour des puces MAPS futures. Enfin, la radiorésistance des puces MAPS avec des nouveaux procédés disponibles est étudiée, et les travaux futurs sont proposés. / Monolithic Active Pixel Sensors (MAPS) are good candidates to be used in High Energy Physics (HEP) experiments for charged particle detection. In the HEP applications, MAPS chips are placed very close to the interaction point and are directly exposed to harsh environmental radiation. This thesis focuses on the study and improvement of the MAPS radiation hardness. The main radiation effects and the research progress of MAPS are studied firstly. During the study, the SRAM IP cores built in MAPS are found limiting the radiation hardness of the whole MAPS chips. Consequently, in order to improve the radiation hardness of MAPS, three radiation hard memories are designed and evaluated for the HEP experiments. In order to replace the SRAM IP cores, a radiation hard SRAM is developed on a very limited area. For smaller feature size processes, in which the single event upset (SEU) effects get significant, a radiation hard SRAM with enhanced SEU tolerance is implemented by an error detection and correction algorithm and a bit-interleaving storage. In order to obtain higher radiation tolerance and higher circuitry density, a dual-port memory with an original 2-transistor cell is developed and evaluated for future MAPS chips. Finally, the radiation hardness of the MAPS chips using new available processes is studied, and the future works are prospected.