A significant amount of research in the field of stereo vision has been published in the past decade. Considerable progress has been made in improving accuracy of results as well as achieving real-time performance in obtaining those results. Although much of the literature does not address it, many applications are sensitive to the tradeoff between accuracy and speed that exists among stereo vision algorithms. Overall, this work aims to organize existing efforts and encourage new ones in the development of stereo vision algorithms for resource limited systems. It does this through a review of the status quo as well as providing both software and hardware designs of new stereo vision algorithms that offer an efficient tradeoff between speed and accuracy. A comprehensive review and analysis of stereo vision algorithms is provided with specific emphasis on real-time performance and suitability for resource limited systems. An attempt has been made to compile and present accuracy and runtime performance data for all stereo vision algorithms developed in the past decade. The tradeoff in accuracy that is typically made to achieve real-time performance is examined with an example of an existing highly accurate stereo vision that is modified to see how much speedup can be achieved. Two new stereo vision algorithms, GA Spline and Profile Shape Matching, are presented with a hardware design of the latter also being provided, making Profile Shape Matching available to both embedded processor-based and programmable hardware-based resource limited systems.

[pt] Nesse trabalho comparamos o uso da programação reativa estruturada com o uso do ReactiveX no desenvolvimento de aplicações reativas soft real time. Apresentamos implementações de aplicações em Lua que demonstram o uso desses modelos em diferentes situações, destacando as vantagens de cada um. Consideramos também o seu uso combinado em uma mesma aplicação. Além disso, implementamos um módulo que permite utilizar a programação reativa estruturada em Lua e utilizamos o módulo RxLua que implementa o modelo ReactiveX. / [en] In this work we compare the use of structured reactive programming and ReactiveX in the development of reactive soft real time applications. We present application implementations using Lua that demonstrate the use of these models in multiple situations, pointing the advantages of using each one. Another consideration is combining both models in a single application. We also developed a module that allows the use of structured reactive programming in Lua and used the RxLua module which implements the ReactiveX model.

The pursuit of precision and flexibility in satellite missions has led to an increased number of formation flying missions being developed. These systems consist of multiple satellites flying at close distances (from a few kilometres to a few meters) to achieve common objectives. This master thesis delves into the domain of the Guidance, Navigation and Control (GNC) for formation flying satellite systems, aiming to propose a novel architecture of different sets of sensors capable of determining absolute and relative positioning of the formation, ensuring mission success. This research begins by providing an overall status of existing and tested in-space systems. It will be complemented with novel and other systems already tested and promising new technologies in development. The thesis then delves into the design of an absolute and a relative Extended Kalman Filter (EKF) for distributed Synthetic Aperture Radar (SAR) systems implemented as part of an in-house simulator. Concluding with the results when using simulated Global Navigation Satellite Systems (GNSS) data as the filter input. Finally, the thesis will be completed with a trade-off analysis of the sensor systems, which could be used in formation-flying satellite systems in the near future. The outcome of this thesis is a novel proposal of a set of sensors to be brought to space navigation, with a corresponding detailed trade-off analysis. Additionally, to validate some of the sensor systems, an EKF is proposed, implemented and tested with the results from an in-house formation flying simulator. This master thesis report is the outcome of the work done during an internship at the Microwave and Radar Institute of the Deutsche Zentrum für Luft- und Raumfahrt e.V. (DLR) – German Aerospace Center – in Oberpfaffenhofen, Bavaria, Germany.

No description available.

The demands of a modern way of life have changed the way power electronics systems work. For instance, the grid has to provide not only the service of delivering electrical energy but also the communication to enable interactions between customers and enable them to be producers of electrical energy, too. Thus, the smart grid has come into existence. The consequence of the smart grid is that consumers could be “smart.” The most obvious consumers are households, so the houses have to also be smart and must be equipped with various power electronics devices for producing and managing electrical energy. Again, all those devices have to communicate somehow and provide data for managing electrical energy in the house. Zoomed in further, novel, state-of-the-art measurement equipment could have been built from different power electronics devices, and communication among them would be necessary for good operation. Zoomed further in, communication among different pieces of power electronics devices (such as converters) could offer benefits such as flexibility, abstraction, and modularity. This thesis provides insight into different communication techniques and protocols used in power electronics systems. A top-down approach presents three different levels of communication used in real-life projects with all the challenges they bring, starting with the smart house, followed by the state-of-the-art impedance measurement unit, and finalizing with internal power electronics building block (PEBB) communication. In the case of a smart house, where the house is equipped with solar panels, charge controllers, batteries, and inverters, communication allows interoperation between different elements of the power electronics system, enabling energy management. Results show the operation of the system and energy management algorithm. A house of this type won first prize at an international competition where energy management was one of the disciplines. The impedance measurement unit consists of different power electronics devices. In this case, too, communication between devices enables the operation of the impedance measurement unit. Communication techniques used here are shown together with measurement results. Finally, inter-PEBB communication has been shown as an approach for interaction among the different elements inside the PEBB, such as controller, GDs, sensors, and actuators. Real-time communication protocol, including all challenges, is described and developed. This approach is shown to enable communication and synchronization among different nodes inside the PEBB. Communication enables all internal elements of the PEBB to be transparent outside the PEBB in the sense that data gathered from them could be reused anywhere else in the system. Also, this approach enables the development of distributed event (time) driven control, hardware and software, abstraction, high modularity, and flexibility. A very important aspect of inter-PEBB communication is synchronization. A simple technique of sharing a clock among the parts of a 6 kV PEBB has been shown. / M.S. / This thesis provides insight into different communication techniques and protocols used in power electronics systems. A top-down approach presents three different levels of communication used in real-life projects with all the challenges they bring, starting with the smart house and a custom device designed and developed to be a communication interface among different power electronics devices from different vendors, such as charge controllers or inverters, but with capabilities not only to communicate but to also provide a platform for the development of energy management algorithms used to make houses grid zero if not grid positive. Aside from the smart house, this thesis describes communication protocols and techniques used in the impedance measurement unit (IMU). This complex measurement device provides valuable and accurate impedance measurements and consists of different power electronics devices that need to communicate. Finally, at the power electronics building block (PEBB) level, real-time communication protocol with all challenges is described. Developed communication protocol provides communication and synchronization among different nodes such as GDs, sensors, and actuators inside the PEBB. This intra-PEBB communication and synchronization combined with inter-PEBB communication and synchronization provide the foundation for the development of truly distributed event- (time-) driven control as well as hardware and software abstraction.

No description available.

Master of Science / Department of Diagnostic Medicine/Pathobiology / T. G. Nagaraja / Shiga toxin-producing E. coli O157 is a major foodborne pathogen. The organism colonizes the hindgut of cattle and is shed in the feces, which serves as a source of contamination of food. Generally, cattle shed E. coli O157 at low concentrations (≤ 10[superscript]2 CFU/g), but a subset of cattle, known as “super-shedders”, shed high concentrations (>10[superscript]3 CFU/g) and are responsible for increased transmission between animals and subsequent hide and carcass contamination. Therefore, concentration data are an important component of quantitative microbial risk assessment. A four-plex quantitative PCR (mqPCR) targeting rfbE[subscript]O157, stx1, stx2 and eae was developed and validated to detect and quantify E. coli O157 in cattle feces. Additionally, the applicability of the assay to detect E. coli O157 was compared to conventional PCR (cPCR) targeting the same four genes, and a culture method. Specificity of the assay to differentially detect the four genes was confirmed. In cattle feces spiked with pure cultures, detection limits were 2.8 x 10[superscript]4 and 2.8 x 10[superscript]0 CFU/g before and after enrichment, respectively. Detection of E. coli O157 in feedlot cattle fecal samples (n=278) was compared between mqPCR, cPCR, and a culture method. Of the 100 samples that were randomly picked from the 136 mqPCR-positive samples, 35 and 48 tested positive by cPCR and culture method, respectively. Of the 100 samples randomly chosen from the 142 mqPCR-negative samples, all were negative by cPCR, but 21 samples tested positive by the culture method. McNemar’s chi-square tests indicated significant disagreement between the proportions of positive samples detected by the three methods. Applicability of the assay to quantify E. coli O157 was determined with feedlot cattle fecal samples (n=576) and compared to spiral plate method. Fecal samples that were quantifiable for O157 by mqPCR (62/576; 10.8%) were at concentrations of ≥ 10[superscript]4 CFU/g of feces. Only 4.5% (26/576) of samples were positive by spiral plate method, with the majority (17/26; 65.4%) at below 10[superscript]3 CFU/g. In conclusion, the mqPCR assay that targets four genes is a novel and more sensitive method than the cPCR or culture method to detect and quantify E. coli O157 in cattle feces.

The focus of this thesis is on specialising the configuration of a field-programmable gate array (FPGA) to allow dynamic reconfiguration of real-time applications. The dynamic reconfiguration of an application has numerous advantages, but due to the overhead introduced by this process, it is only advantageous if the execution time exceeds reconfiguration time. This implies that dynamic reconfiguration is more suited to quasi-static applications, and real-time applications are therefore typically not reconfigured. A method proposed in the literature to ameliorate the overhead from the configuration process is to use a block-RAM (BRAM) based, hardware-controlled reconfiguration architecture, eliminating the need for a processor bus by storing the configuration in localised memory. The drawback of this architecture is the limited size of the BRAM, implying only a subset of configurations can be stored. The work presented in this thesis aim to address this size limitation by proposing a specialiser capable of adapting the configuration stored in the BRAM to represent different sets of hardware. This is done by directly manipulating the bits in the configuration using passive hardware. This not only allows the configuration to be specialised practically immediately, but also allows this specialiser to be device independent. By incorporating this specialiser into the BRAM-based architecture, this study sets out to establish that it is possible to reduce the overhead of the reconfiguration process to such an extent that dynamic reconfiguration can be used for real-time applications. Since the composition of the configuration is not publicly available, a method had to be found to parse and analyse the configuration in order to map the configuration space of the device. The approach used was to compare numerous different configurations and mapping the differences. By analysing these differences, it was found that there is a logical relationship between the slice coordinates and the configuration space of the device. The encoding of the lookup tables was also determined from their initialisation parameters. This allows the configuration of any lookup table to be changed by simply changing the corresponding bits in the configuration. Using this proposed reconfiguration architecture, a distributed multiply-accumulate was reconi figured and its functional density measured. The reason for selecting this specific application is because the multiply-accumulate instruction can be found at the heart of many real-time applications. If the functional density of the reconfigured application is comparable to those of its static equivalent, a strong case can be made for real-time reconfiguration in general. Functional density is an indication of the composite benefits dynamic reconfiguration obtains above its static generic counterpart. Due to the overhead of the reconfiguration process, the functional density of reconfigured applications is traditionally significantly lower than those of static applications. If the functional density of the reconfigured application can rival those of the static equivalent, the overhead from the reconfiguration process becomes negligible. Using this metric, the functional density of the distributed multiply-accumulate was compared for different reconfiguration implementations. It was found that the reconfiguration architecture proposed in this thesis yields a significant improvement over other reconfiguration methods. In fact, the functional density of this method rivalled that of its static equivalent, implying that it is possible to dynamically reconfigure a real-time application. It was also found that the proposed architecture reduces specialisation and reconfiguration time to such an extent that it is possible complete the reconfiguration process within strict time constraints. Even though the proposed method is only capable of reconfiguring the LUTs of a real-time application, this is the first step towards allowing full reconfiguration of applications with dynamic characteristics. The first contribution this thesis makes is a novel method to parse and analyse the configuration of a XilinxR VirtexR -5 FPGA. It also successfully maps the configuration space to the configuration data. Even though this method is applied to a specific device, it is device independent and can easily be applied to any other FPGA. The second contribution comes from using the information obtained from this analysis to design and implement a configuration specialiser, capable of adapting lookup tables in real time. Lastly, the third contribution combines this specialiser with the BRAM-based architecture to allow the reconfiguration of applications typically not reconfigured. / PhD (Computer and Electronic Engineering), North-West University, Potchefstroom Campus, 2015

The focus of this thesis is on specialising the configuration of a field-programmable gate array (FPGA) to allow dynamic reconfiguration of real-time applications. The dynamic reconfiguration of an application has numerous advantages, but due to the overhead introduced by this process, it is only advantageous if the execution time exceeds reconfiguration time. This implies that dynamic reconfiguration is more suited to quasi-static applications, and real-time applications are therefore typically not reconfigured. A method proposed in the literature to ameliorate the overhead from the configuration process is to use a block-RAM (BRAM) based, hardware-controlled reconfiguration architecture, eliminating the need for a processor bus by storing the configuration in localised memory. The drawback of this architecture is the limited size of the BRAM, implying only a subset of configurations can be stored. The work presented in this thesis aim to address this size limitation by proposing a specialiser capable of adapting the configuration stored in the BRAM to represent different sets of hardware. This is done by directly manipulating the bits in the configuration using passive hardware. This not only allows the configuration to be specialised practically immediately, but also allows this specialiser to be device independent. By incorporating this specialiser into the BRAM-based architecture, this study sets out to establish that it is possible to reduce the overhead of the reconfiguration process to such an extent that dynamic reconfiguration can be used for real-time applications. Since the composition of the configuration is not publicly available, a method had to be found to parse and analyse the configuration in order to map the configuration space of the device. The approach used was to compare numerous different configurations and mapping the differences. By analysing these differences, it was found that there is a logical relationship between the slice coordinates and the configuration space of the device. The encoding of the lookup tables was also determined from their initialisation parameters. This allows the configuration of any lookup table to be changed by simply changing the corresponding bits in the configuration. Using this proposed reconfiguration architecture, a distributed multiply-accumulate was reconi figured and its functional density measured. The reason for selecting this specific application is because the multiply-accumulate instruction can be found at the heart of many real-time applications. If the functional density of the reconfigured application is comparable to those of its static equivalent, a strong case can be made for real-time reconfiguration in general. Functional density is an indication of the composite benefits dynamic reconfiguration obtains above its static generic counterpart. Due to the overhead of the reconfiguration process, the functional density of reconfigured applications is traditionally significantly lower than those of static applications. If the functional density of the reconfigured application can rival those of the static equivalent, the overhead from the reconfiguration process becomes negligible. Using this metric, the functional density of the distributed multiply-accumulate was compared for different reconfiguration implementations. It was found that the reconfiguration architecture proposed in this thesis yields a significant improvement over other reconfiguration methods. In fact, the functional density of this method rivalled that of its static equivalent, implying that it is possible to dynamically reconfigure a real-time application. It was also found that the proposed architecture reduces specialisation and reconfiguration time to such an extent that it is possible complete the reconfiguration process within strict time constraints. Even though the proposed method is only capable of reconfiguring the LUTs of a real-time application, this is the first step towards allowing full reconfiguration of applications with dynamic characteristics. The first contribution this thesis makes is a novel method to parse and analyse the configuration of a XilinxR VirtexR -5 FPGA. It also successfully maps the configuration space to the configuration data. Even though this method is applied to a specific device, it is device independent and can easily be applied to any other FPGA. The second contribution comes from using the information obtained from this analysis to design and implement a configuration specialiser, capable of adapting lookup tables in real time. Lastly, the third contribution combines this specialiser with the BRAM-based architecture to allow the reconfiguration of applications typically not reconfigured. / PhD (Computer and Electronic Engineering), North-West University, Potchefstroom Campus, 2015

Advanced embedded systems can consist of many sensors, actuators and processors that are deployed on one or several boards, while having a demand of interacting with each other and sharing resources. Communication between different components usually has strict timing constraints. There is thus a strong need to provide solutions for time critical communication. This thesis focuses on both the support of real-time services over standard switched Ethernet networks and the improvement of systems' real-time characteristics, such as reducing delay and jitter in processors and on communication links. Switched Ethernet has been chosen in this work because of its major advantages in industry; it supports higher bit-rates than most other current LAN (Local Area Network) technologies, including field buses, still at a low cost. We propose using a star network topology with a single Ethernet switch. Each node is connected to a separate port of the switch via a full-duplex link, thereby eliminating collisions. A solid real-time communication protocol for switched Ethernet networks is proposed in the thesis, including a real-time layer between the Ethernet layer and the TCP/IP suite. The network has the capability of supporting both real-time and non real-time traffic and assuring adaptation to the surrounding protocol standards. Most embedded systems work in a dynamic environment, where the precise behavior of the network traffic can usually not be predicted. To support real-time services, we have chosen the Earliest Deadline scheduling algorithm (EDF) because of its optimality, high efficiency and suitability for being used in adaptive schemes. To be able to increase the amount of guaranteed real-time traffic, the notion of Asymmetric Deadline Partitioning Scheme (ADPS) is introduced. ADPS allows distribution of the end-to-end deadline of a message, sent from any source node in the network to any destination node via the switch, into two sub-deadlines, one for each hop according to the load of the physical link that it must traverse. For the EDF scheduling algorithm, the feasibility test is one of the most important techniques that provides us with information about whether or not the real-time traffic can be guaranteed by the network. With the same computational complexity as the feasibility test, a method has been developed to compute the minimum EDF-feasible deadline for a real-time task. The importance of this method in real-time applications lies in that it can be effectively used to reduce the response times of specific control activities or limit their input-output jitter. To allow more flexibility in the control of delay and jitter in real-time systems, a general approach for reducing task deadlines according to the requirements of individual tasks has been developed. The method allows the user to specify a deadline reduction factor for each task in order to better exploit the available slack according to the tasks' actual requirements. / <p>Ingår även i serien: Technical report. D / Department of Computer Science and Engineering, Chalmers University of Technology, 1653-1787 ; 28</p>