O gênero Hantavírus está incluído na família Bunyaviridae que são vírus emergentes associados a roedores que podem infectar o homem causando graves doenças. Nas Américas, os Hantavírus causam uma síndrome pulmonar e cardiovascular (SPCVH) com alta letalidade. Cerca de 1600 casos de SPCVH já foram notificados no Brasil causando mais de 600 óbitos. Sete espécies de Hantavírus são conhecidas no Brasil incluindo o vírus Araraquara que circula nas regiões de cerrado do país associado ao roedor Necromys lasiurus. Para o desenvolvimento de uma RT-PCR em tempo real para detecção e quantificação de Hantavírus, mostramos as etapas para o desenvolvimento de uma one-step RT-PCR em tempo real SYBR Green I para Hantavírus Araraquara que se mostrou específica para o gênero e capaz de detectar até 10 cópias por mL de RNA viral na amostra. Além disso, realizamos um estudo filogenético utilizando algoritmos bayesianos, com 190 sequências completas do gene da nucleoproteína, oriundas de 30 países durante um período de 25 anos (1985-2010) que encontravam-se disponíveis no GenBank (NCBI). Baseando-se em uma taxa média de 6.8 x 10-4 (2.5 x 10-4 - 1 x 10-3) substituições nucleotídicas por sítio/ano, foi possível inferir que os Hantavírus teriam aproximadamente 1917 anos. O processo de dispersão dos Hantavírus pelo mundo teria ocorrido há aproximadamente 500 anos, e a introdução destes vírus nas Américas teria ocorrido há 549 anos (95% HPD 1555-341 anos), via América Central ou México, originando os Hantavírus adaptados aos roedores da subfamília Neotominae, e pelo Brasil surgindo há 406 anos (95% HPD 1150-250 anos) os Hantavírus associados a roedores da subfamília Sigmodontinae, e posteriormente dispersaram para todo o continente sul-americano. O trabalho contribui de forma relevante para o diagnóstico das infecções por Hantavírus com a one-step RT-PCR em tempo real SYBR Green I e também, contribui para o entendimento da filogenia e história destes vírus, oferecendo subsídios ao entendimento sobre como teria ocorrido o espalhamento dos Hantavírus pelo mundo. / The genus Hantavirus is included in the family Bunyaviridae are viruses emerging carried by rodents, which can infect humans causing serious illness. In the Americas, the Hantavirus causing a pulmonary syndrome (HPS) with high lethality. About 1,600 cases of HPS have been reported in Brazil, cause over 1600 deaths. Seven species of Hantavirus are known in Brazil, including Araraquara virus circulating in Cerrado regions (or Savannah regions) of the related in rodents Necromys lasiurus. The development of a real-time RT-PCR for detection and quantitation of Araraquara virus, here we show the steps for developing a one-step SYBR Green real-time RT-PCR for virus Araraquara which proved to be specific for the genus and capable of detecting up to 10 copies of viral RNA per ml in the sample. Furthemore, we performed a phylogenetic analysis using Bayesian algorithms, with 190 complete sequences of the nucleoprotein gene, originating from 30 countries over a 25 year period (1985-2010) that were available in GenBank (NCBI). Based on an average rate of 6.8 x 10-4 (2.5 x 10-4 - 1 x 10-3) nucleotide substitutions per site/year, it was possible to infer that the Hantavirus would be about 1917 years old. The Hantavirus spreading in the world have occurred for nearly 500 years, and the introduction of these viruses have occurred in the Americas 549 years ago (95 years% HPD 1555-341) bye Central America or Mexico, causing the Hantavirus adapted to rodents subfamily Neotominae, and Brazil emerged 406 years ago (95% HPD 1150-250 years) the Hantavirus associated with rodents subfamily Sigmodontinae, and subsequently disseminated to South America. The work contributes significantly to the diagnosis of Hantavirus infections with one-step SYBR Green real-time RT-PCR and also contributes to an understanding of the phylogeny and evolutionary history of these viruses, offering subsidies have occurred understanding of how the Hantavirus spread of the worldwide.

Em relação aos significativos resultados em Qualidade de Serviço (QoS) para servidores Web, existem ainda muitos problemas não resolvidos. Enquanto as abordagens atuais se limitam a prover QoS relativa através de diferenciação de serviço, este projeto apresenta e compara três modelos que tem por objetivo prover QoS absoluta para um array de servidores Web heterogêneos por meio de uma arquitetura de escalonamento ortogonal: A Multiple Queue (MQ), a Single Queue (SQ) e a Dynamic Single Queue (DSQ). A MQ consiste em receber a requisição HTTP e enviá-la para o servidor escolhido do array de servidores através do balanceamento de carga. A SQ e a DSQ possuem uma única fila gerenciada de forma centralizada. Enquanto a SQ envia a requisição somente quando o servidor esta livre, a DSQ seleciona o servidor com mais curto tempo de término mediante o uso de filas virtuais. Os modelos foram simulados considerando diferentes parâmetros e configurações para o ambiente. A avaliação de desempenho da arquitetura ortogonal demonstra que a mesma provê um bom desempenho na provisão de QoS absoluta com relação as mudanças instantâneas das cargas de trabalho no ambiente Web. Esta pesquisa estende os resultados da politica de escalonamento chamada EBS, concebida para provisão de garantias de tempo de resposta estocásticas em ambientes interativos online, especificamente para os servidores Web. Os resultados demonstram que a combinação da EBS na política de fila com a disciplina de recurso proposta neste trabalho é superior às outras combinações examinadas. Um modelo de política adaptativa é também introduzido / Despite the significant body of results in Quality of Service (QoS) for Web-Servers, many real-world problems are not easily supported. While the current approaches limit to provide relative QoS through service differentiation, this work presents and compares three models aiming at providing absolute QoS to Web Server on heterogeneous cluster by means of an Orthogonal Scheduling Architecture: The Multiple Queue (MQ), the Single Queue (SQ) and the Dynamic Single Queue (DSQ). The MQ consists in receiving the HTTP requests and delivering them for the selected processor in the server array to balance the load. SQ and DSQ have only one queue being managed by a central server. While SQ sends requests to the first free processors, the DSQ selects the processor with the minimun completion time with the aid of a virtual queue. The models were simulated considering different parameters and configurations for the environment. Performance evaluation of the Orthogonal Architecture demonstrates that it performs well in providing absolute QoS in face of instantaneous changes in the workloads. This work extends the results of a scheduling policy named EBS, tailored for providing stochastic response-time guarantees in online interactive systems, specifically for Web servers. Results show that the combination of EBS as the queue discipline with the resource discipline proposed in this work outperforms the other studied. An adaptive policy model is also introduced

O ciclo estral das cadelas difere das demais espécies domésticas. Estudos demonstraram que o aumento da concentração plasmática de P4 durante a fase luteínica das cadelas pode levar a alterações metabólicas como a resistência insulínica, acarretando complicações como Diabetes mellitus. A glicose é uma molécula transportada, na maioria das células, por proteínas transportadoras. O processo de instalação da resistência insulínica é caracterizado por alterações teciduais da expressão de algumas proteínas transportadoras de glicose, como o GLUT4. Atualmente 13 isoformas de proteínas transportadoras já foram seqüenciadas (GLUT1 ao GLUT13). O GLUT4 está presente nos músculos e no tecido adiposo, principalmente. Para avaliar se a expressão do GLUT 4 está presente nas células luteínicas e se esta expressão relaciona-se à produção de P4 e E2, 28 cadelas foram divididas em 7 grupos de acordo com os dias após a ovulação -p.o. (de 10 à 70 dias, n = 4 por grupo). Os ovários foram dissecados e congelados em nitrogênio líquido, o RNA extraído e o cDNA confeccionado e submetido ao PCR em tempo real. O gene GAPDH foi utilizado como controle endógeno para padronização da expressão do gene alvo. Foi coletado sangue para dosagem da glicemia, insulinemia, progesterona e estradiol. Para avaliar a regulação positiva do GLUT4 avaliamos também a expressão do mRNA do HIF-1α, destas mesmas cadelas. A expressão do GLUT4 apresentou tendência a aumento de expressão aos 20 dias (p. o.), quando comparado aos 10, 30 e 40 dias, pico de expressão aos 50 dias (p.o.), e então apresentou tendência a queda aos 60 e 70 dias p.o. Já a expressão do HIF-1α manteve-se muito semelhante através dos dias, tendendo a queda aos 10 e aos 40 dias pós ovulação, quando comparado com os demais grupos. Os resultados de dosagem de P4 e E2 variaram dentro do esperado para o diestro e não apresentaram correlação com a expressão de GLUT 4; a glicemia e insulina, aqui expressas através do índice HOMA (insulina x glicose % 22,5), apresentou pico aos 40 dias. Sabe-se que quanto mais alto o índice HOMA, menos este animal é sensível à insulina, ou seja, mais resistente à ela. Observou-se que o índice HOMA apresentou-se mais alto aos 40 dias, associado aos menores valores de expressão do GLUT4. Por outro lado, obtivemos o pico de expressão de GLUT4 aos 50 dias, quando o índice HOMA apresentou valores baixos. Sugere-se que a queda da P4 associada à elevação do estradiol plasmático possa influenciar o índice HOMA. Pode-se concluir que a expressão do GLUT4 no corpo lúteo de cadelas segue o padrão observado para tecidos sensíveis à insulina, nos quais existe uma maior expressão durante a fase de maior sensibilidade à insulina e diminuição drástica em fase de pré ou já instalada resistência insulínica. / The canine estral cycle differs from other domestic species. Some studies demonstrated that the increase of the plasmatic concentration of progesterone during canine luteinic phase can lead to metabolic alterations, such as insulinic resistance and may cause complications such as Diabetes mellitus. Glucose is a molecule that is transported in most cells by transporting proteins. The process of installation of the insulinic resistance is characterized by tissue alterations of the expression of some glucose transporting proteins, as GLUT4. Currenly, 13 isoforms of transporting proteins were sequenced (GLUT1 to GLUT13). GLUT4 is present mainly in muscle and fat tissue. In order to assess if GLUT4 expression is present in luteal cells, and if this expression is related to P4 and E2 production, 28 bitches were divided into 7 groups, in accordance with the days after the ovulation -p.o. (from 10 to 70 days, n=4 for group). The ovaries were dissected and frozen in liquid nitrogen. The RNA was extracted and the cDNA was made and submitted to real time PCR. GAPDH gene was used as endogenous conntrol to standardization of target gene expression. Blood was collected to glycemia, insulinemia, P4, and E2β dosage. To assess the positive regulation of GLUT4, we also assessed HIF-1α mRNA expression of the same bitches. GLUT4 expression showed a tendency to increase the expression on the twentieth day (p.o.), when compared to the 10th, 30th, and 40th days, expression top on the 50 th day (p.o.) , and then, it showed a tendency to foll on the 60th and 70th days p.o. HIF-1α expression was very similar over the days, tending to fall on the 10th and 40th days post ovulation, when compared to other groups. P4 and E2β dosage results varied according to thr expectations in diestrus and have not shown correlation with GLUT4 expression; glycemia and insulin, here expressed by HOMA index (insulin x glucose % 22,5) showed crest (highest point) on the 40 th day. It is knows that the higher the HOMA index, the less sensitive this animal is to insulin, it is, more resistant to it. It was observed that HOMA index was higher on the 40th day, associated to small values of the GLUT4 expression. Otherwise, the got the top of GLUT4 expression on the 50th day, when HOMA index showed low values. It has been suggested that P4 fall associated to the plasmatic E2 increase may influence HOMA index. We may conclude that GLUT4 expression into the corpus luteum of bitches follows the standard observed in insulin-sensitive tissues, in which there is a higher expression over the phase of higher sensitiveness to insulin and remarkable decrease in pre or even installed insulinic resistance.

Sistemas embarcados ganham cada vez mais espaço devido ao aumento da demanda por novas funções em equipamentos, às normas regulatórias e às novas necessidades dos consumidores e do mercado. Esse aumento nos requisitos aumenta o tamanho e a complexidade dos softwares embarcados cuja importância cresce significativamente. Sistemas operacionais de tempo real constituem uma ferramenta poderosa para gerenciar a complexidade, facilitar o reuso e aumentar a portabilidade do software e também reduzir o time-to-market. Este trabalho visa avaliar a aplicabilidade de sistemas operacionais de tempo real em sistemas embarcados de baixo custo que utilizam microprocessadores pequenos (8 e 16 bits), avaliando suas características e propondo as melhores alternativas para desenvolvimento de software embarcado. Para o atendimento desta proposta, foi realizado o levantamento de características sobre o desenvolvimento brasileiro de sistemas embarcados, uma análise das características de sistemas de pequeno porte, uma discussão da viabilidade do uso de RTOS e um estudo de caso comparando arquiteturas de software embarcado. Os resultados principais mostram que arquiteturas simplificadas como a Superloop apresentam vantagem sobre os sistemas operacionais devido ao baixo consumo de memória e processamento. Os sistemas operacionais, apesar de propiciarem desenvolvimentos de códigos modulares bem como facilitar o gerenciamento de tempo, são de difícil implementação em microcontroladores pequenos, devido ao seu elevado consumo de memória e processamento. O uso de sistemas operacionais é viável para sistemas de pequeno porte com no mínimo 4 Kbytes de memória RAM e processos com limite de tempo máximo para execução (deadlines) superiores a 1 ms, condições essas que evitam a sobrecarga do microcontrolador. Neste trabalho também é mostrado um retrato do desenvolvimento de embarcados no Brasil. / Embedded systems, more and more are gaining importance, due to the increase of features requested on equipments, the regulatory standards and the costumers and market requirements. This increment on requirements increases the software size and complexity, which importance significantly grows. Real-time operating systems represents a powerful tool to manage the complexity, help the software reuse and improve portability of the software and also reduce the time-to-market. This work aims to analyze the real-time operating systems, verifying their application on low cost embedded systems using small microcontrollers (8 and 16-bit), evaluating their characteristics and propose the best architectures for software development. To attend this proposal, it was performed a survey of Brazilian embedded system development, evaluates the low cost embedded system characteristics, discusses the viability of RTOS usage and performs a comparative study of embedded software architectures. Results show that simplified architectures like the Superloop presents vantages over the operating systems due to their low memory and processing consumption. The operating system, besides helping on time management and code modularity, is difficult to implement in small microcontrollers, due to the high memory and processing consumption. The operating systems are more applicable to small embedded systems with at minimum 4 Kbytes of RAM memory and process with maximum execution time (deadlines) over 1 ms, conditions that do not causes microcontroller overload. In this work is also presented an overview of Brazilian embedded system development.

Esta tese estuda modificações no sistema operacional Linux para a arquitetura x86 da Intel, com a finalidade de aumentar o desempenho, nessa plataforma, das aplicações de processamento digital de sinais em tempo real. Inicialmente são estabelecidos requisitos para um sistema operacional voltado para o processamento digital de sinais. Os requisitos são estabelecidos com base na estrutura dos programas de processamento digital de sinais em tempo real e nas situações mais comuns nesse tipo de processamento. Um fator chave quando se trata de processamento em tempo real é a latência para colocar o aplicativo em execução. Nesse contexto, o trabalho desenvolve um modelo para a latência no tratamento das interrupções externas no Linux. Usando esse modelo é desenvolvido um método para medir as várias componentes dessa latência, método este baseado na colocação de marcadores de tempo no núcleo do Linux. O método de medida proposto é usado para medir a latência do Linux no tratamento de uma interrupção externa em três condições diferentes. O estudo finaliza propondo, implementando e testando alterações no Linux que visam melhorar o desempenho, desse sistema, em aplicações de processamento digital de sinais em tempo real. / This work studies modifications in the Linux operating system for the Intel x86 architecture, with the purpose of increasing the performance in applications of digital signal processing in real-time. Initially the requirements for a digital signal processing operating systems are established. These requirements are based on the structure of the programs of digital signal processing in real-time and the most common situations in this type of processing. An important factor in real-time processing is the latency to put the process in execution. In this context, this work develops a latency model for the I/O interrupts handling in Linux. By using this model, a method is developed to measure components of this latency. This measurement method is based on time markers collocated in the Linux kernel. The proposed method is used to measure the Linux latency for an I/O interrupt handling in three different conditions. Finally this research proposes, implements and tests alterations in Linux with the purpose of increasing the performance of this operating system in applications of digital signal processing in real-time.

by Zhao Lei. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 78-85). / Abstracts in English and Chinese. / Abstract --- p.ii / Acknowledgments --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Background --- p.5 / Chapter 2.1 --- Agents --- p.5 / Chapter 2.1.1 --- Deliberative Agents --- p.7 / Chapter 2.1.2 --- Reactive Agents --- p.8 / Chapter 2.1.3 --- Interacting Agents --- p.9 / Chapter 2.1.4 --- Hybrid Architectures --- p.10 / Chapter 2.2 --- Real-time Artificial Intelligence --- p.10 / Chapter 2.3 --- Real-Time Agents --- p.12 / Chapter 2.3.1 --- The Subsumption Architecture --- p.13 / Chapter 2.3.2 --- The InterRAP Architecture --- p.15 / Chapter 2.3.3 --- The 3T Architecture --- p.16 / Chapter 2.4 --- On-line Scheduling in Real-Time Agents --- p.18 / Chapter 3 --- A Real-Time Agent Architecture --- p.20 / Chapter 3.1 --- Human Cognition Model --- p.20 / Chapter 3.1.1 --- Perception --- p.22 / Chapter 3.1.2 --- Cognition --- p.22 / Chapter 3.1.3 --- Action --- p.23 / Chapter 3.2 --- Real-Time Message Passing Primitives and Process Structuring --- p.24 / Chapter 3.2.1 --- Message Passing as IPC --- p.25 / Chapter 3.2.2 --- Administrator and Worker Processes --- p.28 / Chapter 3.3 --- Agent Architecture --- p.29 / Chapter 3.3.1 --- Sensor Workers and the Sensor Administrator --- p.30 / Chapter 3.3.2 --- The Cognition Workers --- p.32 / Chapter 3.3.3 --- "The Task Administrator, the Scheduler Worker and Ex- ecutor Workers" --- p.32 / Chapter 3.4 --- An Agent-Based Real-time Arcade Game --- p.34 / Chapter 4 --- A Multiple Method Approach to Task Scheduling --- p.37 / Chapter 4.1 --- Task Scheduling Mechanism --- p.37 / Chapter 4.1.1 --- Task and Action --- p.38 / Chapter 4.1.2 --- Task Administrator --- p.40 / Chapter 4.1.3 --- Task Scheduler --- p.43 / Chapter 4.2 --- A Task Scheduling Model --- p.44 / Chapter 4.3 --- Combination Rules and Special Cases --- p.46 / Chapter 4.4 --- Scheduling Algorithms --- p.49 / Chapter 5 --- Task Scheduling Model: Analysis and Experiments --- p.53 / Chapter 5.1 --- Goodness Measure --- p.53 / Chapter 5.2 --- Theoretical Analysis --- p.54 / Chapter 5.3 --- Implementation --- p.59 / Chapter 5.3.1 --- Task Generator Implementation --- p.59 / Chapter 5.3.2 --- Executor Workers Implementation --- p.61 / Chapter 5.4 --- Experimental Results --- p.62 / Chapter 5.4.1 --- Hybrid Mechanism and Individual Algorithms --- p.63 / Chapter 5.4.2 --- Effect of Average Execution Time --- p.65 / Chapter 5.4.3 --- Effect of the Greedy Algorithm --- p.65 / Chapter 5.4.4 --- Effect of the Advanced Algorithm --- p.67 / Chapter 5.4.5 --- Effect of Actions and Relations Among Them --- p.68 / Chapter 5.4.6 --- Effect of Deadline --- p.71 / Chapter 6 --- Conclusions --- p.73 / Chapter 6.1 --- Summary of Contributions --- p.73 / Chapter 6.2 --- Future Work --- p.75

by Patrick C.K. Wu. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 57-[59]). / Abstract also in Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Research Objectives --- p.2 / Chapter 1.2 --- Organization of the Thesis --- p.2 / Chapter 2 --- Background --- p.4 / Chapter 2.1 --- Reliable Multicasting --- p.4 / Chapter 2.2 --- Related Work --- p.5 / Chapter 2.2.1 --- RMTP --- p.5 / Chapter 2.2.2 --- RMP --- p.6 / Chapter 2.2.3 --- RAMP --- p.7 / Chapter 2.3 --- Multicast with Scalable Reliability (MSR) --- p.8 / Chapter 3 --- Traffic Shaping in MSR --- p.10 / Chapter 3.1 --- Single Queue System --- p.11 / Chapter 3.2 --- Scaling factor α --- p.12 / Chapter 4 --- Retransmission Scheme in MSR --- p.15 / Chapter 4.1 --- Packet Loss Detection and Requests for Retransmission at the Receivers --- p.17 / Chapter 4.2 --- Retransmission at the Sender --- p.19 / Chapter 4.3 --- Dynamic Adjustment of Retransmission Timeout Value --- p.22 / Chapter 4.4 --- Scaling Reliability using Transmit-Display Window --- p.29 / Chapter 5 --- NACK Implosion Prevention --- p.31 / Chapter 5.1 --- Electing a Representative Receiver --- p.32 / Chapter 5.2 --- Determining T --- p.33 / Chapter 5.3 --- Determining β --- p.34 / Chapter 6 --- Performance Study of MSR --- p.38 / Chapter 6.1 --- Performance Study of MSR in Simple Network Topologies --- p.39 / Chapter 6.2 --- Star Topology --- p.40 / Chapter 6.3 --- Tree Topology --- p.44 / Chapter 6.4 --- Exploring the use of MSR Gateway --- p.47 / Chapter 7 --- Conclusion and Future Work --- p.50 / Chapter 7.1 --- Future Work --- p.50 / Chapter 7.2 --- Conclusions --- p.51 / Chapter A --- MSR Packet Formats --- p.52 / Chapter A.1 --- MSR Fixed Header --- p.52 / Chapter A.2 --- MSR Audio Data Header --- p.54 / Chapter A.3 --- MSR NACK Packets --- p.55 / Bibliography --- p.57

by Walter Chi-Woon Fung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 64-[67]). / Abstract also in Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Limitation of Existing Research --- p.3 / Chapter 1.3 --- Contributions of This Thesis --- p.3 / Chapter 1.4 --- Organization of the Thesis --- p.4 / Chapter 2 --- Related Work --- p.5 / Chapter 2.1 --- Ongoing Efforts For The Support of Real Time Applications on the Internet - RTP --- p.5 / Chapter 2.2 --- Using the Algorithm on top of RTP --- p.7 / Chapter 3 --- An Adaptive Video Retrieval Algorithm --- p.9 / Chapter 3.1 --- Lossless Environment --- p.9 / Chapter 3.1.1 --- Adapting the Request Rate to the Available Bandwidth --- p.12 / Chapter 3.2 --- Lossy Environment --- p.17 / Chapter 3.2.1 --- Adapting Ar in Lossy Environment --- p.20 / Chapter 3.3 --- Adjusting the Window Size --- p.24 / Chapter 3.4 --- Measurement Issues --- p.27 / Chapter 3.5 --- Mapping between Data Rate and Frame Rate --- p.28 / Chapter 4 --- Rate Measurement --- p.30 / Chapter 4.1 --- Arrival Rate Estimation --- p.30 / Chapter 4.2 --- Loss Rate Estimation --- p.32 / Chapter 5 --- Frame Skipping and Stuffing --- p.37 / Chapter 5.1 --- MPEG-1 Video Stream Basics --- p.37 / Chapter 5.2 --- Frame Skipping --- p.38 / Chapter 5.3 --- Frame Stuffing In Lossy Environment --- p.40 / Chapter 6 --- Experiment Result and Analysis --- p.43 / Chapter 6.1 --- Experiment --- p.43 / Chapter 6.2 --- Analysis --- p.54 / Chapter 6.2.1 --- Interacting With Streams With No Rate Control --- p.56 / Chapter 6.2.2 --- Multiple Streams Running The Algorithm --- p.58 / Chapter 6.2.3 --- Calculation of p --- p.59 / Chapter 7 --- Conclusions --- p.61 / Bibliography --- p.64

Fleissner Sebastian. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (leaves 91-95). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- The Legend of Hercules --- p.1 / Chapter 1.2 --- Background --- p.2 / Chapter 1.3 --- Research Purpose --- p.2 / Chapter 1.4 --- Research Overview --- p.3 / Chapter 1.5 --- Thesis Organization --- p.4 / Chapter 2 --- Background and Definitions --- p.6 / Chapter 2.1 --- General Purpose GPU Computing --- p.6 / Chapter 2.1.1 --- Four Generations of GPU Hardware --- p.6 / Chapter 2.1.2 --- GPU Architecture & Terms --- p.7 / Chapter 2.1.3 --- General Purpose GPU Programming --- p.9 / Chapter 2.1.4 --- Shader Programming Languages --- p.12 / Chapter 2.2 --- Cryptography Overview --- p.13 / Chapter 2.2.1 --- "Alice, Bob, and Friends" --- p.14 / Chapter 2.2.2 --- Cryptographic Hash Functions --- p.14 / Chapter 2.2.3 --- Secret Key Ciphers --- p.15 / Chapter 2.2.4 --- Public Key Encryption --- p.16 / Chapter 2.2.5 --- Digital Signatures --- p.17 / Chapter 2.3 --- The Montgomery Method --- p.18 / Chapter 2.3.1 --- Pre-computation Step --- p.19 / Chapter 2.3.2 --- Obtaining the Montgomery Representation --- p.19 / Chapter 2.3.3 --- Calculating the Montgomery Product(s) --- p.19 / Chapter 2.3.4 --- Calculating final result --- p.20 / Chapter 2.3.5 --- The Montgomery Exponentiation Algorithm . . --- p.20 / Chapter 2.4 --- Elliptic Curve Cryptography --- p.21 / Chapter 2.4.1 --- Introduction --- p.21 / Chapter 2.4.2 --- Recommended Elliptic Curves --- p.22 / Chapter 2.4.3 --- Coordinate Systems --- p.23 / Chapter 2.4.4 --- Point Doubling --- p.23 / Chapter 2.4.5 --- Point Addition --- p.24 / Chapter 2.4.6 --- Double and Add --- p.25 / Chapter 2.4.7 --- Elliptic Curve Encryption --- p.26 / Chapter 2.5 --- Related Research --- p.28 / Chapter 2.5.1 --- Secret Key Cryptography on GPUs --- p.28 / Chapter 2.5.2 --- Remotely Keyed Cryptographics --- p.29 / Chapter 3 --- Proposed Algorithms --- p.30 / Chapter 3.1 --- Introduction --- p.30 / Chapter 3.2 --- Chapter Organization --- p.31 / Chapter 3.3 --- Algorithm Design Issues --- p.31 / Chapter 3.3.1 --- Arithmetic Density and GPU Memory Access . --- p.31 / Chapter 3.3.2 --- Encoding Large Integers with Floating Point Numbers --- p.33 / Chapter 3.4 --- GPU Montgomery Algorithms --- p.34 / Chapter 3.4.1 --- Introduction --- p.34 / Chapter 3.4.2 --- GPU-FlexM-Prod Specification --- p.37 / Chapter 3.4.3 --- GPU-FlexM-Mul Specification --- p.43 / Chapter 3.4.4 --- GPU-FlexM-Exp Specification --- p.45 / Chapter 3.4.5 --- GPU-FixM-Prod Specification --- p.46 / Chapter 3.4.6 --- GPU-FixM-Mul Specification --- p.50 / Chapter 3.4.7 --- GPU-FixM-Exp Specification --- p.52 / Chapter 3.5 --- GPU Elliptic Curve Algorithms --- p.54 / Chapter 3.5.1 --- GPU-EC-Double Specification --- p.55 / Chapter 3.5.2 --- GPU-EC-Add Specification --- p.59 / Chapter 3.5.3 --- GPU-EC-DoubleAdd Specification --- p.64 / Chapter 4 --- Analysis of Proposed Algorithms --- p.67 / Chapter 4.1 --- Performance Analysis --- p.67 / Chapter 4.1.1 --- GPU-FlexM Algorithms --- p.69 / Chapter 4.1.2 --- GPU-FixM Algorithms --- p.72 / Chapter 4.1.3 --- GPU-EC Algorithms --- p.77 / Chapter 4.1.4 --- Summary --- p.82 / Chapter 4.2 --- Usability of Proposed Algorithms --- p.83 / Chapter 4.2.1 --- Signcryption --- p.84 / Chapter 4.2.2 --- Pure Asymmetric Encryption and Decryption --- p.85 / Chapter 4.2.3 --- Simultaneous Signing of Multiple Messages --- p.86 / Chapter 4.2.4 --- Relieving the Main Processor --- p.87 / Chapter 5 --- Conclusions --- p.88 / Chapter 5.1 --- Research Results --- p.88 / Chapter 5.2 --- Future Research --- p.89 / Bibliography --- p.91

Quality-of-service (QoS) requirements for the timely delivery of real-time multimedia raise new challenges for the networking world. A key component of QoS is QoS routing which allows the selection of network routes with sufficient resources for requested QoS parameters. Several techniques have been proposed in the literature to compute QoS routes, most of which require dynamic update of link-state information across the Internet. Given the growing size of the Internet, it is becoming increasingly difficult to gather up-to-date state information in a dynamic environment. We propose a new technique to compute QoS routes on the Internet in a fast and efficient manner without any need for dynamic updates. Our method, known as Selective Flooding, checks the state of the links on a set of pre-computed routes from the source to the destination in parallel and based on this information computes the best route and then reserves resources. We implemented Selective Flooding on a QoS routing simulator and evaluated the performance of Selective Flooding compared to source routing for a variety of network parameters. We find Selective Flooding consistently outperforms source routing in terms of call-blocking rate and outperforms source routing in terms of network overhead for some network conditions. The contributions of this thesis include the design of a new QoS routing algorithm, Selective Flooding, extensive evaluation of Selective Flooding under a variety of network conditions and a working simulation model for future research.