Tanto nos circuitos integrados para processamento de sinais digitais quanto em microprocessadores, a parte operativa é o núcleo onde a computação dos dados é realizada. A geração deste bloco costuma ser crítica para o desempenho global dos dispositivos. Ferramentas específicas para a geração de parte operativa costumam tirar proveito da regularidade estrutural do circuito para produzir leiautes mais densos e com melhor desempenho. Este trabalho apresenta um novo fluxo de projeto para geração de parte operativa onde foi desenvolvido um gerador automático de leiaute de células CMOS com suporte à lógica não-complementar e um compilador de parte operativa. O uso destas duas ferramentas permite a rápida prototipação de uma biblioteca inteira de células lógicas otimizadas, para atender diferentes requisitos de desempenho, que em seguida são utilizadas para montagem de cada um dos blocos funcionais da parte operativa pelo compilador. Comparações feitas com a ferramenta de síntese de células lógicas mostraram que a metodologia desenvolvida é capaz de produzir resultados similares em área e tempo de geração que métodos exatos e ainda possui a vantagem de suportar o uso de múltiplas métricas de qualidade durante o posicionamento dos transistores. As células geradas automaticamente apresentaram acréscimo de área médio de apenas 14% quando comparado às standard-cells e com resultado de atraso e consumo de potência muito próximos ou melhores. Circuitos de parte operativa foram gerados automaticamente pelo compilador e apresentaram na média, menor área, consumo de potência e atraso que circuitos gerados com um fluxo de síntese automático para standard-cells. / Datapath is the core where all the computations are performed in circuits for digital signal processing and also in microprocessors. The performance of the whole system is frequently determined by the implementation of the datapath. Tools dedicated for synthesis of this unit are called datapath compilers and use to take advantage on the structural regularity of the circuit to produce dense layouts and with good performance. This work presents a new flow for datapath generation. An automatic cell synthesis tool with support to non-complementary logic is used in conjunction with a datapath compiler to achieve timing optimization and technology independence. The cell library produced as result of the synthesis process is used by the compiler to place the cells and generate each one of the datapath operators. Comparisons with other cell sythesis tools shown that our approach was able to produce results comparable in area and generation time. Automatically generated cells were compared to standard-cell layouts and presented an average area overhead of just 14% while our circuits presented better or very close delay and power consumption. The datapaths produced by the compiler were compared to a traditional standard-cell based synthesis design flow and presented smaller area, delay and power consumption in average than this approach.

For the on-chip bus, flexibility is the key to reuse by enabling developers to select the optimal architecture to efficiently meet the performance requirements of a wide variety of systems. AMBA is an open standard, on-chip bus specification that details a strategy for the interconnection and management of functional blocks that makes up a System-on-Chip (SoC). AMBA will let designers multiply the total bandwidth available in a system without changing the bus interface on existing intellectual property (IP) cores. Sometimes, the SoC designer to select the optimal combination of bus frequency (to match the peripherals) and number of channels (to achieve the bandwidth), using the AMBA Multi-layer architecture. The AHB of the AMBA System Bus connects embedded processors such as an ARM core to high-performance peripherals, DMA controllers, on-chip memory and interfaces. It is a high-speed, high-bandwidth bus that supports multi-master bus management to maximize system performance. In this thesis, we implement an software, Automatic Generation of On-Chip Bus Infrastructure for SoC, and it supports the AMBA AHB, Multi-layer AHB architecture to optimize system bandwidth, or AHB-Lite to streamline single master layers. By user set up, it can generate the relative on-chip bus infrastructure. We use each AHB Monitor of SDV and Synposys to validate the protocol of infrastructure respectively. In Test Patterns, we use Bus Functional Model to verify all type transfers of bus. In hardware implement, we use SYS32TM, SYS32TME, SYS16TM, and MEMCU to integrate three type AHBs. Every example, we also build FPGA prototyping and chip layout. We do this to validate our on-chip bus infrastructure.

The main focus of this research is to use graph-theoretic formulations to develop an automated algorithm for the generation of sensitivity equations. The idea is to combine the benefits of direct differentiation with that of graph-theoretic formulation. The primary deliverable of this work is the developed software module which can derive the system equations and the sensitivity equations directly from the linear graph of the system. Sensitivity analysis refers to the study of changes in system behaviour brought about by the changes in model parameters. Due to the rapid increase in the sizes and complexities of the models being analyzed, it is important to extend the capabilities of the current tools of sensitivity analysis, and an automated, efficient, and accurate method for the generation of sensitivity equations is highly desirable. In this work, a graph-theoretic algorithm is developed to generate the sensitivity equations. In the current implementation, the proposed algorithm uses direct differentiation to generate sensitivity equations at the component level and graph-theoretic methods to assemble the equation fragments to form the sensitivity equations. This way certain amount of control can be established over the size and complexity of the generated sensitivity equations. The implementation of the algorithm is based on a commercial software package \verb MapleSim[Multibody] and can generate governing and sensitivity equations for multibody models created in MapleSim. In this thesis, the algorithm is tested on various mechanical, hydraulic, electro-chemical, multibody, and multi-domain systems. The generated sensitivity information are used to perform design optimization and parametric importance studies. The sensitivity results are validated using finite difference formulations. The results demonstrate that graph-theoretic sensitivity analysis is an automated, accurate, algorithmic method of generation for sensitivity equations, which enables the user to have some control over the form and complexity of the generated equations. The results show that the graph-theoretic method is more efficient than the finite difference approach. It is also demonstrated that the efficiency of the generated equations are at par or better than the equation obtained by direct differentiation.

Tanto nos circuitos integrados para processamento de sinais digitais quanto em microprocessadores, a parte operativa é o núcleo onde a computação dos dados é realizada. A geração deste bloco costuma ser crítica para o desempenho global dos dispositivos. Ferramentas específicas para a geração de parte operativa costumam tirar proveito da regularidade estrutural do circuito para produzir leiautes mais densos e com melhor desempenho. Este trabalho apresenta um novo fluxo de projeto para geração de parte operativa onde foi desenvolvido um gerador automático de leiaute de células CMOS com suporte à lógica não-complementar e um compilador de parte operativa. O uso destas duas ferramentas permite a rápida prototipação de uma biblioteca inteira de células lógicas otimizadas, para atender diferentes requisitos de desempenho, que em seguida são utilizadas para montagem de cada um dos blocos funcionais da parte operativa pelo compilador. Comparações feitas com a ferramenta de síntese de células lógicas mostraram que a metodologia desenvolvida é capaz de produzir resultados similares em área e tempo de geração que métodos exatos e ainda possui a vantagem de suportar o uso de múltiplas métricas de qualidade durante o posicionamento dos transistores. As células geradas automaticamente apresentaram acréscimo de área médio de apenas 14% quando comparado às standard-cells e com resultado de atraso e consumo de potência muito próximos ou melhores. Circuitos de parte operativa foram gerados automaticamente pelo compilador e apresentaram na média, menor área, consumo de potência e atraso que circuitos gerados com um fluxo de síntese automático para standard-cells. / Datapath is the core where all the computations are performed in circuits for digital signal processing and also in microprocessors. The performance of the whole system is frequently determined by the implementation of the datapath. Tools dedicated for synthesis of this unit are called datapath compilers and use to take advantage on the structural regularity of the circuit to produce dense layouts and with good performance. This work presents a new flow for datapath generation. An automatic cell synthesis tool with support to non-complementary logic is used in conjunction with a datapath compiler to achieve timing optimization and technology independence. The cell library produced as result of the synthesis process is used by the compiler to place the cells and generate each one of the datapath operators. Comparisons with other cell sythesis tools shown that our approach was able to produce results comparable in area and generation time. Automatically generated cells were compared to standard-cell layouts and presented an average area overhead of just 14% while our circuits presented better or very close delay and power consumption. The datapaths produced by the compiler were compared to a traditional standard-cell based synthesis design flow and presented smaller area, delay and power consumption in average than this approach.

Este trabalho apresenta o desenvolvimento de um fluxo de projeto de circuitos digitais integrados, visando a incluir células geradas automaticamente pela ferramenta ASTRAN. Como parte integrante deste novo fluxo, desenvolveu-se uma nova técnica de comparação entre células, utilizando Redes Neurais Artificiais, para a modelagem das células ASTRAN, esta técnica se mostrou flexível ao se adaptar a diversos tipos de células e com resultados robustos tendo 5% de desvio padrão e 4% para o erro relativo. Também, foi criada uma ferramenta capaz de substituir células comerciais por células ASTRAN, tendo como objetivo melhorar as características de potência consumida e área utilizada pelo circuito, e por fim gerando um circuito misto composto de células comerciais feitas à mão e células ASTRAN geradas automaticamente. O foco principal deste trabalho encontra-se na integração do fluxo de geração de células geradas automaticamente a um fluxo de síntese comercial de circuitos digitais. Os resultados obtidos mostraram-se promissores, obtendo-se ganhos em redução de área e potência dos circuitos analisados. Em média os circuitos tiveram uma redução de 3,77% na potência consumida e 1,25% menos área utilizada. Com um acréscimo de 0,64% por parte do atraso total do circuito. / This work presents the development of a design flow for digital integrated circuits, including cells generated automatically by the ASTRAN tool. Moreover, a new technique, using Artificial Neural Networks, was developed to perform a comparison between two different cells, i.e. commercial and ASTRAN’s cell. This technique proved to be flexible when adapting to several types of cells and with robust results having 5% of standard deviation and 4% for relative error. Also, a new tool was developed, capable of performing cell replacement between ASTRAN and commercial cells, to improve power consumption an used area. Finally a mixed circuit composed of handmade commercial cells and cells automatically generated by ASTRAN was generated. A target was to mix an automatic cell synthesis tool with commercial synthesis tools dedicated to standard cells. Comparisons have shown that our approach was able to produce satisfactory results related area and power consumption. In average the circuits had a reduction of 3.77% in the power consumed and 1.25% less used area. With an increase of 0.64% due to the total delay of the circuit.

Tanto nos circuitos integrados para processamento de sinais digitais quanto em microprocessadores, a parte operativa é o núcleo onde a computação dos dados é realizada. A geração deste bloco costuma ser crítica para o desempenho global dos dispositivos. Ferramentas específicas para a geração de parte operativa costumam tirar proveito da regularidade estrutural do circuito para produzir leiautes mais densos e com melhor desempenho. Este trabalho apresenta um novo fluxo de projeto para geração de parte operativa onde foi desenvolvido um gerador automático de leiaute de células CMOS com suporte à lógica não-complementar e um compilador de parte operativa. O uso destas duas ferramentas permite a rápida prototipação de uma biblioteca inteira de células lógicas otimizadas, para atender diferentes requisitos de desempenho, que em seguida são utilizadas para montagem de cada um dos blocos funcionais da parte operativa pelo compilador. Comparações feitas com a ferramenta de síntese de células lógicas mostraram que a metodologia desenvolvida é capaz de produzir resultados similares em área e tempo de geração que métodos exatos e ainda possui a vantagem de suportar o uso de múltiplas métricas de qualidade durante o posicionamento dos transistores. As células geradas automaticamente apresentaram acréscimo de área médio de apenas 14% quando comparado às standard-cells e com resultado de atraso e consumo de potência muito próximos ou melhores. Circuitos de parte operativa foram gerados automaticamente pelo compilador e apresentaram na média, menor área, consumo de potência e atraso que circuitos gerados com um fluxo de síntese automático para standard-cells. / Datapath is the core where all the computations are performed in circuits for digital signal processing and also in microprocessors. The performance of the whole system is frequently determined by the implementation of the datapath. Tools dedicated for synthesis of this unit are called datapath compilers and use to take advantage on the structural regularity of the circuit to produce dense layouts and with good performance. This work presents a new flow for datapath generation. An automatic cell synthesis tool with support to non-complementary logic is used in conjunction with a datapath compiler to achieve timing optimization and technology independence. The cell library produced as result of the synthesis process is used by the compiler to place the cells and generate each one of the datapath operators. Comparisons with other cell sythesis tools shown that our approach was able to produce results comparable in area and generation time. Automatically generated cells were compared to standard-cell layouts and presented an average area overhead of just 14% while our circuits presented better or very close delay and power consumption. The datapaths produced by the compiler were compared to a traditional standard-cell based synthesis design flow and presented smaller area, delay and power consumption in average than this approach.

Este trabalho apresenta o desenvolvimento de um fluxo de projeto de circuitos digitais integrados, visando a incluir células geradas automaticamente pela ferramenta ASTRAN. Como parte integrante deste novo fluxo, desenvolveu-se uma nova técnica de comparação entre células, utilizando Redes Neurais Artificiais, para a modelagem das células ASTRAN, esta técnica se mostrou flexível ao se adaptar a diversos tipos de células e com resultados robustos tendo 5% de desvio padrão e 4% para o erro relativo. Também, foi criada uma ferramenta capaz de substituir células comerciais por células ASTRAN, tendo como objetivo melhorar as características de potência consumida e área utilizada pelo circuito, e por fim gerando um circuito misto composto de células comerciais feitas à mão e células ASTRAN geradas automaticamente. O foco principal deste trabalho encontra-se na integração do fluxo de geração de células geradas automaticamente a um fluxo de síntese comercial de circuitos digitais. Os resultados obtidos mostraram-se promissores, obtendo-se ganhos em redução de área e potência dos circuitos analisados. Em média os circuitos tiveram uma redução de 3,77% na potência consumida e 1,25% menos área utilizada. Com um acréscimo de 0,64% por parte do atraso total do circuito. / This work presents the development of a design flow for digital integrated circuits, including cells generated automatically by the ASTRAN tool. Moreover, a new technique, using Artificial Neural Networks, was developed to perform a comparison between two different cells, i.e. commercial and ASTRAN’s cell. This technique proved to be flexible when adapting to several types of cells and with robust results having 5% of standard deviation and 4% for relative error. Also, a new tool was developed, capable of performing cell replacement between ASTRAN and commercial cells, to improve power consumption an used area. Finally a mixed circuit composed of handmade commercial cells and cells automatically generated by ASTRAN was generated. A target was to mix an automatic cell synthesis tool with commercial synthesis tools dedicated to standard cells. Comparisons have shown that our approach was able to produce satisfactory results related area and power consumption. In average the circuits had a reduction of 3.77% in the power consumed and 1.25% less used area. With an increase of 0.64% due to the total delay of the circuit.

Esta dissertação investiga o processo de conversão automática de textos estruturados para hiperdocumentos. Analisa vantagens e desvantagens da utilização de um processo automático. Faz um levantamento detalhado das etapas envolvidas nesta conversão. Como resultado da pesquisa propõe um processo de conversão baseado em definições formais da estrutura dos documentos e das citações. O domínio de aplicação do processo de conversão é o conjunto de normas estatutárias jurídicas brasileiras. Outro resultado deste trabalho é a ferramenta WebifyLaw que implementa o processo de conversão automática para o conjunto das normas estatutárias jurídicas brasileiras. Os resultados da aplicação da WebifyLaw na Constituição Federal, no Código Civil e no Código de Processo Civil e em outras 42 normas são apresentados e discutidos. / This work centered in the research of the automatic conversion of structured texts into hyperdocuments. It presents an analysis concerning the advantages and disadvantages of such automatic process. It also details the steps involved in this conversion. As one of the results it proposes an automatic conversion process, which is based on document structure and citations´ formal definitions. The application domain is set as Brazilian statutory norms. Another contribution from this work is a tool called WebifyLaw, which implements the automatic conversion process for the chosen domain. The tool was applied to the Brazilian Constitution, the Civil Code among other 42 norms. The results obtained in using this application are also presented and discussed.

I nästan alla moderna datorspel så återfinns datorstyrda karaktärer, vilka behöver kunna navigera i spelvärlden. Dessa karaktärer kan vara olika typer av fiender i ett förstapersonskjutarspel, eller motståndare och medhjälpare i ett sportspel (exempelvis fotboll- eller rallyspel) med mera. Det finns många tekniker för att realisera vägplanering och det kan vara stora skillnader, både prestandamässiga och funktionella, mellan dem. Detta arbete jämför två olika sökrymdsrepresentationer för vägplanering, nämligen vägpunktsgrafer och navigationsnät, där sökrymderna automatgenererats. Jämförelsen görs med ett experiment och avser såväl prestanda (tids- och minneskostnad) som funktionalitet (optimal väg och antal svängar). Experimentmiljön stödjer godtyckliga vägar och ger detaljerad statistik för en noggrann jämförelse av vägplaneringsteknikerna. Arbetet visar på att navigationsnätet presterar bäst vad gäller funktionalitet. Vad gäller prestanda så presterar navigationsnätet generellt sett bäst, men vägpunktsgrafen kan ge bättre prestanda om nodavståndet hålls relativt högt. Det finns också många möjligheter att vidareutveckla arbetet, exempelvis förfina vägarna och kombinera vägplaneringsteknikerna med robotik.

This research focuses on frequency control ancillary services in large interconnected systems. It analyses and assesses possible alternatives for optimal and innovative solutions of major frequency control issues in large interconnected systems within liberalised electricity markets. Possible improvements in the performance of frequency control are identified. A framework of frequency control ancillary services in large interconnected systems by including loads and wind generation is also proposed.The research has been motivated by the paucity of research in power system dynamics focusing on large interconnected systems such as the European synchronous system and the Eastern interconnection which experience important frequency control challenges. These challenges include:- Decline in frequency response in the Eastern interconnection - Deterministic frequency deviations observed at the top of the hours in the European synchronous systemFrequency control issues became critical when electricity markets were deregulated and frequency control became an ancillary service with a decidedly commercial focus. This commercial focus has spawned a lot of work on frequency control markets and economics whereas not much research has been devoted to dynamic simulation of large interconnected systems. Apart from this commercial focus, frequency control in large interconnected systems is still based on historical practices mainly because changes suggested in the literature can be barely applied in large interconnected systems. This is essentially because dynamic simulation studies are uncorrelated with frequency control markets and economics. More specifically, dynamic studies do not take into account the characteristics of each reserve activated and also the way the reserve is activated. With the deregulation of the electricity market, reserve is considered as a product and not necessarily a response provided by a unit. The main objectives of this research therefore are to solve critical frequency control issues in large interconnected deregulated electricity systems, which may present potential economic benefits. To achieve these objectives, frequency control in large interconnected systems is studied by considering on one hand frequency control theory and on the other hand its implementation in practice taking account of frequency control ancillary service markets as well as the economics and practical consequences of frequency control. This approach is necessary to accommodate the future evolution of frequency control in large interconnected systems. The proposed approach is illustrated through a model of frequency control in the European synchronous system, where practices are better known, are clearly standardised and also where frequency data has been obtained.