Computed tomography (CT) is routinely used for diagnosing lung disease and developing treatment plans using images of intricate lung structure with submillimeter resolution. Automated segmentation of anatomical structures in such images is important to enable efficient processing in clinical and research settings. Convolution neural networks (ConvNets) are largely successful at performing image segmentation with the ability to learn discriminative abstract features that yield generalizable predictions. However, constraints in hardware memory do not allow deep networks to be trained with high-resolution volumetric CT images. Restricted by memory constraints, current applications of ConvNets on volumetric medical images use a subset of the full image; limiting the capacity of the network to learn informative global patterns. Local patterns, such as edges, are necessary for precise boundary localization, however, they suffer from low specificity. Global information can disambiguate structures that are locally similar. The central thesis of this doctoral work is that both local and global information is important for segmentation of anatomical structures in medical images. A novel multi-scale ConvNet is proposed that divides the learning task across multiple networks; each network learns features over different ranges of scales. It is hypothesized that multi-scale ConvNets will lead to improved segmentation performance, as no compromise needs to be made between image resolution, image extent, and network depth. Three multi-scale models were designed to specifically target segmentation of three pulmonary structures: lungs, fissures, and lobes. The proposed models were evaluated on a diverse datasets and compared to architectures that do not use both local and global features. The lung model was evaluated on humans and three animal species; the results demonstrated the multi-scale model outperformed single scale models at different resolutions. The fissure model showed superior performance compared to both a traditional Hessian filter and a standard U-Net architecture that is limited in global extent. The results demonstrated that multi-scale ConvNets improved pulmonary CT segmentation by incorporating both local and global features using multiple ConvNets within a constrained-memory system. Overall, the proposed pipeline achieved high accuracy and was robust to variations resulting from different imaging protocols, reconstruction kernels, scanners, lung volumes, and pathological alterations; demonstrating its potential for enabling high-throughput image analysis in clinical and research settings.

Autonomous vehicles have many application possibilities within many different fields like rescue missions, exploring foreign environments or unmanned vehicles etc. For such system to navigate in a safe manner, high requirements of reliability and security must be fulfilled. This master's thesis explores the possibility to use the machine learning algorithm convolutional network on a robotic platform for autonomous path following. The only input to predict the steering signal is a monochromatic image taken by a camera mounted on the robotic car pointing in the steering direction. The convolutional network will learn from demonstrations in a supervised manner. In this thesis three different preprocessing options are evaluated. The evaluation is based on the quadratic error and the number of correctly predicted classes. The results show that the convolutional network has no problem of learning a correct behaviour and scores good result when evaluated on similar data that it has been trained on. The results also show that the preprocessing options are not enough to ensure that the system is environment dependent.

In this thesis, we present an FPGA implementation of parallel-node low-density-parity-check convolutional-code (PN-LDPC-CC) encoder and decoder. A 2.4 Gbit/s rate-1/2 (3, 6) PN-LDPC-CC encoder and decoder were implemented on an Altera development and education board (DE4). Detailed power measurements of the FPGA board for various configurations of the design have been conducted to characterize the power consumption of the decoder module. For an Eb/N0 of 5 dB, the decoder with 9 processor cores (pipelined decoder iteration stages) has a bit-error-rate performance of 10E-10 and achieves an energy-per-coded-bit of 1.683 nJ based on raw power measurement results. The increase in Eb/N0 can effectively reduce the decoder power and energy-per-coded-bit for configurations with 5 or more processor cores for Eb/N0 < 5 dB. The incremental decoder power cost and incremental energy-per-coded-bit also hold a linearly decreasing trend for each additional processor core. Additional experiments are performed to account for the effect of the efficiency of the DC/DC converter circuitry on the raw power measurement data. Further experiments have also been conducted to quantify the effect of clipping thresholds, bit width for each processor core on bit-error-rate (BER) performance, power consumption, and logic utilization of the decoder. A “6Core" decoder with growing bit-width log-likelihood ratios (LLRs) has been found to have a BER performance near that of a “6Core" 6-bit decoder while consuming similar power, and logic utilization to that of a 5-bit “6Core" decoder.

In wireless communication system, convolutional coding method is often used to encode the data. In decoding convolutional code (CC), Viterbi algorithm is considered to be the best mechanism. Viterbi decoder (VD) was developed to execute the algorithm on mobile devices more effectively. This decoder is often used on 2G and 3G mobile phones. However, on 2G phones, VD consumes about one third of total power consumption of the signal receiver. Therefore it is very necessary to reduce the power consumption of VD on 2G and 3G phones. VD uses large amount of register in survivor metric unit (SMU), so that the decoder can receive enough CC and converge automatically. The goal of this thesis is to decrease power consumption of SMU by using path metric compare unit (PMCU) to find the best state of path metric unit (PMU). This way decreases half of registers and multiplexers required in SMU, leading to significant area reduction in decoder. During the process of signal transmission in wireless communication, different causes like the atmosphere, outer space radiation and man-made will interfere the signal by different degree. The stronger the noise is, the more interference CC will get. The error detection circuit used will mark the sections with noise interference before the CC enters the VD. If CC is interfered, it will be decoded by the whole VD. Otherwise, it will be decoded by low power decoder, where the controller will start clock gating mechanism on SMU to close up unnecessary power consumption block. The power consumption of is varying proposed Adaptive Viterbi decoder according to the interference degree. When interference degree is high, the power consumption is 21% less than conventional VD; when interference is low, it is 44% less. The results show that the proposed method can effectively reduce the power consumption of VD.

In this thesis, a highly efficient implementation of the channel decoder for terrestrial digital video broadcast (DVBT) standard is proposed. DVB-T channel decoder is mainly composed of four major modules including the inner Viterbi decoder, outer Reed-Solomon decoder and inner and outer de-interleaver modules which all require significant amount of intermediate data storage. The main contribution of this thesis is to propose suitable architectural solution for each individual module to achieve efficient realization of the data storage mostly by single-port memory blocks which can lead to the reduction of silicon area and the dynamic power dissipation. For the outer convolutional deinterleaver module, a special address generator has been proposed such that the data deinterleaver path can be merged and implemented as three memory blocks. For the inner symbol deinterleaver module, a lookahead technique has been applied to the design of address generator that can generate valid deinterleaving address each cycle to avoid the buffering problem. In addition, a novel deinterleaver memory partitioning architecture is proposed such that the entire deinterleaver can be built on four single-port memory banks. These four modules have been verified and integrated as a robust channel decoder silicon intellectual property (IP). Our implementation result shows that the core area of entire DVB-T channel decoder IP (Intellectual Property) can be realized in less than 6.8 mm2 in 0.18-&#x00B5;m TSMC technology.

In this thesis, we consider decentralized multiclass classification problem in wireless sensor networks. In literature, the decentralized detection using error correcting code has been shown to have good fault-tolerance capability. In this thesis, we provide fault-tolerance capability by employing the code with a particular structure so that the decoding at the fusion center can be efficient. Specifically, the convolution code is employed to decode the local decision vector sent from all the local sensors. In addition, we proposed an efficient convolution code design algorithm by using simulated annealing. The simulation result shows that the proposed approach has good performance.

Transmit diversity usually employs multiple antennas at the transmitter. However, many wireless devices such as mobile cellphones, Personal Digital Assistants (PDAs), just to name a few, are limited by size, hardware complexity, power and other constraints to just one antenna. A new paradigm called cooperative communication which allows single antenna mobiles in a multi-user scenario to share their antennas has been proposed lately. This multi-user configuration generates a virtual Multiple-Input Multiple-Output system, leading to transmit diversity. The basic approach to cooperation is for two single-antenna users to use each other's antenna as a relay in which each of the users achieves diversity. Previous cooperative signaling methods encompass diverse forms of repetition of the data transmitted by the partner to the destination. A new scheme called coded cooperation [15] which integrates user cooperation with channel coding has also been proposed. This method maintains the same code rate, bandwidth and transmit power as a similar non-cooperative system, but performs much better than previous signaling methods [13], [14] under various inter-user channel qualities. This dissertation first discusses the coded cooperation framework that has been proposed lately [19], coded cooperation with Repeat Convolutional Punctured Codes (RCPC) codes and then investigates the application of turbo codes in coded cooperation. In this dissertation we propose two new cooperative diversity schemes which are the Repeat-Punctured Turbo Coded cooperation and coded cooperation using a Modified Repeat-Punctured Turbo Codes. Prior to that, Repeat-Punctured Turbo codes are introduced. We characterize the performance of the two new schemes by developing the analytical bounds for bit error rate, which is confirmed by computer simulations. Finally, the turbo coded cooperation using the Forced Symbol Method (FSM) is presented and validated through computer simulations under various inter-user Signal-to-Noise Ratios (SNRs). / Thesis (M.Sc.Eng.)-University of KwaZulu-Natal, 2008.

In this thesis, we present an FPGA implementation of parallel-node low-density-parity-check convolutional-code (PN-LDPC-CC) encoder and decoder. A 2.4 Gbit/s rate-1/2 (3, 6) PN-LDPC-CC encoder and decoder were implemented on an Altera development and education board (DE4). Detailed power measurements of the FPGA board for various configurations of the design have been conducted to characterize the power consumption of the decoder module. For an Eb/N0 of 5 dB, the decoder with 9 processor cores (pipelined decoder iteration stages) has a bit-error-rate performance of 10E-10 and achieves an energy-per-coded-bit of 1.683 nJ based on raw power measurement results. The increase in Eb/N0 can effectively reduce the decoder power and energy-per-coded-bit for configurations with 5 or more processor cores for Eb/N0 < 5 dB. The incremental decoder power cost and incremental energy-per-coded-bit also hold a linearly decreasing trend for each additional processor core. Additional experiments are performed to account for the effect of the efficiency of the DC/DC converter circuitry on the raw power measurement data. Further experiments have also been conducted to quantify the effect of clipping thresholds, bit width for each processor core on bit-error-rate (BER) performance, power consumption, and logic utilization of the decoder. A “6Core" decoder with growing bit-width log-likelihood ratios (LLRs) has been found to have a BER performance near that of a “6Core" 6-bit decoder while consuming similar power, and logic utilization to that of a 5-bit “6Core" decoder.

Turbo-codes are a popular error correction method for applications requiring bit error rates from 10−3 to 10−6, such as wireless multimedia applications. In order to reduce the complexity of the turbo-decoder, it is advantageous to use the simplest possible constituent codes, such as 4-state recursive systematic convolutional (RSC) codes. However, for such codes, the error floor can be high, thus making them unable to achieve the target bit error range. In this dissertation, two methods of lowering the error floor are investigated. These methods are interleaver selection, and puncturing selective data bits. Through the use of appropriate code design criteria, various types of interleavers, and various puncturing parameters are evaluated. It was found that by careful selection of interleavers and puncturing parameters, a substantial reduction in the error floor can be achieved. From the various interleaver types investigated, the variable s-random type was found to provide the best performance. For the puncturing parameters, puncturing of both the data and parity bits of the turbo-code, as well as puncturing only the parity bits of the turbo-code, were considered. It was found that for applications requiring BERs around 10−3 , it is sufficient to only puncture the parity bits. However, for applications that require the full range of BER values, or for applications where the FER is the important design parameter, puncturing some of the data bits appears to be beneficial. / Graduate

Object recognition systems have significant influences on modern life. Face, iris and finger point recognition applications are commonly applied for the security purposes; ASR (Automatic Speech Recognition) is commonly implemented on speech subtitle generation for various videos and audios, such as YouTube; HWR (Handwriting Recognition) systems are essential on the post office for cheque and postcode detection; ADAS (Advanced Driver Assistance System) are well applied to improve drivers’, passages’ and pedestrians’ safety. Object recognition techniques are crucial and valuable for academia, commerce and industry. Accuracy and efficiency are two important standards to evaluate the performance of recognition techniques. Accuracy includes how many objects can be indicated in real scene and how many of them can be correctly classified. Efficiency means speed for system training and sample testing. Traditional object detecting methods, such as HOG (Histogram of orientated Gradient) feature detector combining with SVM (Support Vector Machine) classifier, cannot compete with frameworks of neural networks in both efficiency and accuracy. Since neural network has better performance and potential for improvement, it is worth to gain insight into this field to design more advanced recognition systems. In this thesis, we list and analyze sophisticated techniques and frameworks for object recognition. To understand the mathematical theory for network design, state-of-the-art networks in ILSVRC (ImageNET Large Scale Visual Recognition Challenge) are studied. Based on analysis and the concept of edge detectors, a simple CNN (Convolutional Neural Network) structure is designed as a trail to explore the possibility to utilize the network of high width and low depth for region proposal selection, object recognition and target region refining. We adopt Le-Net as the template, taking advantage of multi-kernels of GoogLe-Net. We made experiments to test the performance of this simple structure of the vehicle and face through ImageNet dataset. The accuracy for the single object detection is 81% in average and for plural object detection is 73.5%. We refined networks through many aspects to reach the final accuracy 95% for single object detection and 89% for plural object detection.