We present a new circuit design for adaptive offset cancellation in a fully differential 2.4 GHz CMOS direct conversion mixer. Our circuit structure is a modification of a Gilbert cell mixer in which offsets are cancelled by injecting cancellation currents into the legs of the mixer by dynamically varying the bias on the active loads. We present analysis and simulation results of our mixer with offsets present. Offsets create non-linearities in any circuit by differentially shifting the small-signal bias point of a matched pair; forcing once symmetrical transistors to operate in different bias regions and create second order distortion. We focus our design to minimize second order distortion while simultaneously canceling the large offsets found in direct conversion receivers. Simulation results for the mixer canceling a wide range of offsets are included. Our mixer has a gain of 6.4dB, an IIP3 of 17dBm and a noise figure of 17dB as simulated in a .5��m HP Mosis CMOS process. / Graduation date: 2002

Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum sampling frequency allows for an overall sampling frequency of M times the individual converters' sampling rate. However, the performance of interleaved systems suffers from mismatches between the sub-converters. Offset mismatches, gain mismatches, and timing mismatches all contribute to the degradation of the resolution of the ADC system. Offset and gain mismatches can be corrected for in the digital domain with minimal extra processing. However, the effects of timing mismatches (specifically, the magnitude of the spurious tones that are introduced) are dependent on the frequency of the input, so digital correction is not a trivial task. This makes a circuit-based correction mechanism a much more desirable solution to the problem. This work explores the effect of timing mismatches on interleaved analog-to-digital converter performance. A set of requirements is derived to specify the performance of a variable-delay circuit for the tuning of sample clocks. Since the mismatches can be composed of both fixed and random components, several candidate architectures are modeled for their delay and jitter performance. One candidate is selected for design, based on its jitter performance and on practical considerations. A practical implementation of the clock-adjustment circuit is designed, featuring low-noise differential clock paths with high precision delay adjustment. A means of testing the circuit and verifying the precision of adjustment is presented. The design is implemented for fabrication, and post-layout simulations are shown to demonstrate the feasibility and functionality of the design.

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This thesis researchs the design of quadrature modulator consists of 120MHz quadrature modulator that is fabricated using hybrid elements and print circuit board (PCB) technology for digital signal generator and quadrature modulator monolithic-microwave integrated-circuit (MMIC) that is fabricated using GaAs heterojunction bipolar transistor (HBT) technology for Personal Communication Service (PCS) applications. The 120MHz quadrature modulator incorporates power divider/combiner, phase shifter and doubly balanced mixer; the design architecture, principle and measurement results of division are presented in this thesis. A quadrature modulator is implemented by combining every division and measures specifications accurately, comparing with that of Agilent ESG-D series digital signal generator with the same carrier frequency and digital modulation. The quadrature modulator MMIC for PCS applications incorporates phase shifter, Gilbert cell mixer, differential to single-ended converter and RF amplifier at output; the design architecture, principle and simulation results of division are presented in this thesis. A quadrature modulator is integrated by combining every division and simulates parameters strictly.For troublesome specification measurement of quadrature modulator, this thesis also presents measurement method and instrument setup detailedly.

A simple methodology for determining the input referred offset voltage of comparators is presented. This in general is difficult as the output of a comparator is discrete valued. The method relies on a Monte-Carlo-Simulation with certain comparator input values and some postprocessing of the comparator output data. The comparator is always operated in its intended environment, there is no modification of the comparator itself nor some unusual stimuli required. There is also no known restriction for the type of comparators to be analyzed.

Thesis (Ph. D.)--University of Texas at Austin, 2003. / Supervisor: Sanjay K. Banerjee. Vita. Includes bibliographical references. Also available from UMI.

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Detection and monitoring of the damage created by the corrosion of the steel reinforcement in concrete structures is a challenging and multidisciplinary problem. Economical monitoring strategy that is long-term and nondestructive requires low-cost, battery-free, wireless sensors. Our Electronic Structural Surveillance (ESS) platform uses battery-free passive resonant circuit (tag) as a sensor. The tag is magnetically coupled to an external reader coil. It is interrogated/read remotely in a non-contact (wireless) manner and the state of the sensor is determined from a swept frequency impedance measurement. When paired with the correct sensing element (transducer), the tag can be used for a variety of sensing applications for example, chemical & biochemical sensors. A circuit model of the reader and tag for such a universal battery-free wireless sensor platform is developed. The interaction between design and detection limit is examined. The dependence of the measured signal strength and read range on the various reader and tag circuit parameters is analyzed. Since the values of the circuit of the coils are dependent on their geometries, the effect of specific coil geometry is evaluated and design recommendations are made. / text

Amorphous Oxide semiconductors have gained large interest in the display industry owing to their high carrier mobilities and low fabrication costs. In this thesis, n-channel solution based zinc-tin oxide (ZTO) thin-film transistors (TFTs) are studied from a circuit design perspective. The study includes an iterative process of circuit design, layout and test procedure of the fabricated devices in the lab. The device models used in circuit simulations are refined following the data fed back from each of these iterations which has enabled more accurate design of complex circuits using ZTO devices. The requirement and development of a physical compact model for performing accurate and predictive circuit simulations has been presented. The use of ZTO devices in low cost, transparent and flexible electronic applications has been investigated through the study of basic circuit blocks such as amplifiers, ring oscillators, inverters and a four stage Operational Amplifier. / text