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This thesis focuses on the design and implementation of low power Σ∆ ADCs in 130 nanometer CMOS technology. The design issues in the implementation of a third order ADC with a multi-bit and single bit quantizer are discussed. The advancement in CMOS technology has led to designing as much of electronics systems as possible with the digital circuits and digital signal processing replacing analog processing in most cases. Hence there is a need for digitizing analog signals with analog to digital converter (ADC). In communication systems this needs to be done immediately after the antenna in a receiver system. As this is difficult to implement due to high speed and high power consumption, RF signal is converted to a lower intermediate frequency (IF) and digitized. This work stresses low power implementation of high bandwidth Σ∆ ADCs for digitizing the IF. Design techniques involved in the implementation of a third order continuous time Σ∆ ADC with a 4 bit quantizer as well as a single bit quantizer for wide bandwidth are discussed. Moreover, a third order continuous time audio ADC implementation was also done. The behavioural modelling of the Σ∆ ADC along with clock jitter non-linearity model was developed and the issues in circuit design techniques are addressed. The continuous time ADCs’ major problem, namely, excess loop delay is discussed in detail and an efficient compensation technique for the same is implemented which allows a large reduction of power consumed by the ADC. Choice of loop filter architecture, quantizer and transistor level implementation are given that result in better immunity to offsets and process variations. Both the ADCs have been implemented using UMC 130 nm Mixed-mode RF-CMOS process and the simulation results for the multi-bit ADC gives a peak SNR of 56dB with a dynamic range of 65dB with power consumption of 2mW. The audio ADC achieves a peak SNR of 94.2dB with a dynamic range of 91dB.

A new digital receiver was built for the Ooty Radio Telescope (ORT). This new digital receiver system functionally replaces many systems custom-built for various applications at ORT. The thesis presents the receiver design, tests conducted, contributions made, revisions to the receiver architecture and future scopes. The novelty of the receiver design is in treating the ORT as an array of 22 antenna elements. Simulation studies were carried out to analyze the array performance of ORT. The IF signals are digitized and processed by a combination of multiple FPGAs and computers. Major transport of data in the receiver is through high speed serial communication. Programs were developed for configuration, control, data acquisition and off-line analysis. The functionality of the proposed digital receiver was verified through laboratory tests. The proposed receiver enables several new modes of operation of the ORT and field tests were carried out to verify these features of the system. These tests are briefly described below. The radio waves received on earth from celestial sources are extremely weak and their presence can only be detected by sensitive receivers associated with large radio telescopes. The resulting vulnerability of such observations to the ever increasing presence of radio frequency interference has prompted us to to develop new procedures to identify RFI at ORT through time and frequency domain analysis. The digital receiver has also been used in carrying out RFI study at ORT module level for the first time. Our study demonstrates that a major challenge to realizing the full potential of the ORT will be to detect weakly interfering RFI features and occasionally appearing RFI spikes and correct for their contamination in the observations. The examples provided by our analysis of data collected using the digital receiver are very useful for interpreting the data obtained during sensitive spectral line observations and has already enabled several new studies, the most notable being a sensitive recombination line survey conducted using our digital receiver at ORT as part of another research work. A spectral line emission detection procedure using our receiver has been evolved and an example result obtained by observing a region is presented in the thesis. Formation of phased array of ORT modules using the digitized IF signal is discussed and its implementation is verified through observation of celestial sources. An important requirement for proper phasing of the array is the calibration of differential delay/phase variations across the modules of the ORT, for which a powerful method was implemented based on the cross correlation of signals arriving at the 22 modules. This new method employs Hilbert Transform technique to introduce phase information in the sampled signal and the estimated delay and phase corrections are found to be consistent and repeatable. An interplanetary scintillation observation was made with the phased array and the resultant fluctuation spectra obtained are presented. Several pulsar observations and continuum sources have been observed and the results are presented. Another notable feature of the proposed digital receiver is the enhanced field of view which will lead to a reduced observing time observing extended regions. The improved spectral and temporal resolutions have also been demonstrated by the observations presented in the thesis. In particular, the single pulse observations of pulsars reported in the thesis were enabled by the high time resolution supported by the receiver.. The present work also demonstrated the digital beam formation with ORT modules in arbitrary directions. The digitally synthesized beam was compared within the first null positions of the central analog beam (beam-7) of ORT and the result is reported in the thesis. The new digital receiver enabled all the above mentioned analyses which were carried out for the first time at ORT. The results of the field trials emphasized the need for future observations to include RFI monitoring and characterization as part of the observing strategy and continuously evolve the algorithms for RFI mitigation by using different statistical signatures of the celestial signals. The need for providing a layer of buffering and preprocessing before the final beam formation or correlation is emphasized. To facilitate such development in the future, the final operational system provides for software based correlator which can be developed using the algorithms presented in this thesis. This transforms our original target of a reconfigurable platform to a much more flexible re-programmable platform. In particular, this simplifies the application of windowing functions and polyphase filters to control the beam shapes to (a) reduce beam dilution effects and, (b) to enhance RFI rejection by side lobe suppression. Such techniques can be used to reduce spectral leakage and reduce the effect of RFI on adjacent frequency channels in critical observations. Our receiver is adequate for realizing the maximum potential of the IF signals entering the receiver room. Any further enhancement of the ORT spectral coverage and instantaneous sky coverage will require telescope's front end modification and digitization of signals at the RF stage. The real time processing capabilities can be further enhanced by using multi-core processors and multi gigabit ethernet interfaces that are starting to appear as commodity hardware. Thus the present work opens up several new avenues for future work.

Modern wireless communication systems call for ultra wideband operations to meet the continuous growth in the number of users of these systems. Since antenna is an integral part of any wireless communication system (transmitter or receiver), designing antennas with good gain over large bandwidth needs to be considered first. To meet the popular demand, wireless communication systems should be as cheap as possible which require antennas with small size, light weight, low profile and low cost, and that are easy to fabricate and assemble. A type of antenna that satisfies most of these requirements is the microstrip antenna. Most of the wideband techniques for microstrip antennas utilize complicated geometries such as stacked multiple metal/dielectric layers, complicated feed arrangements etc., which elude the primary attraction of microstrip antennas. On the other hand, single layer suspended configurations are considered the best choice as these are simple to fabricate and assemble. The objective of this research is to investigate simple microstrip antennas with large bandwidth. A single layer suspended microstrip configuration was chosen for the purpose. In the first part of the research, the bandwidth was increased to about 50% with linear phase characteristics by optimizing the feed configurations while retaining the overall simplicity. This study has resulted in proposing a criterion for obtaining maximum bandwidth in the suspended microstrip configuration. An analytical model has been developed for such an antenna configuration. Although several analytical tools are available for the microstrip antenna analysis, equivalent circuit based approach proves to be a simple one and offers convincingly accurate results. Another advantage of the proposed equivalent circuit modeling scheme is that it is suitable for computer aided design (CAD). In order to make this approach even more useful, the antenna designed in the first part was modified to meet desired specifications such as reduction in the air gap to make the antenna compact, symmetrical patterns, making antenna circularly polarized (LHCP or RHCP) without changing the feed configuration. Nearly symmetrical patterns were obtained throughout the band of operation by modifying the profile of patch close to the feed strip. Circular polarization (CP) operation has been obtained from the basic antenna by cutting a diagonal slot on the radiator patch. Here the slot orientation decides the type of CP i.e., LHCP or RHCP. In this work obtained of 7.1% axial ratio (3dB) bandwidth with other characteristics unaffected. The overall height of the antenna is reduced by 55% by cutting a slot and re-optimizing the feed strip dimensions. These studies emphasize flexibility offered by the design approach in realizing practical antennas for various applications.

To achieve the goal of efficient ”anytime, anywhere” communication, it is essential to develop mobile devices which can efficiently support multiple wireless communication standards. Also, in order to efficiently accommodate the further evolution of these standards, it should be possible to modify/upgrade the operation of the mobile devices without having to recall previously deployed devices. This is achievable if as much functionality of the mobile device as possible is provided through software. A mobile device which fits this description is called a Software Defined Radio (SDR). Reconfigurable hardware-based solutions are an attractive option for realizing SDRs as they can potentially provide a favourable combination of the flexibility of a DSP or a GPP and the efficiency of an ASIC. The work presented in this thesis discusses the development of efficient reconfigurable hardware for one of the most energy-intensive functionalities in the mobile device, namely, Forward Error Correction (FEC). FEC is required in order to achieve reliable transfer of information at minimal transmit power levels. FEC is achieved by encoding the information in a process called channel coding. Previous studies have shown that the FEC unit accounts for around 40% of the total energy consumption of the mobile unit. In addition, modern wireless standards also place the additional requirement of flexibility on the FEC unit. Thus, the FEC unit of the mobile device represents a considerable amount of computing ability that needs to be accommodated into a very small power, area and energy budget. Two channel coding techniques have found widespread use in most modern wireless standards -namely convolutional coding and turbo coding. The Viterbi algorithm is most widely used for decoding convolutionally encoded sequences. It is possible to use this algorithm iteratively in order to decode turbo codes. Hence, this thesis specifically focusses on developing architectures for flexible Viterbi decoders. Chapter 2 provides a description of the Viterbi and turbo decoding techniques. The flexibility requirements placed on the Viterbi decoder by modern standards can be divided into two types -code rate flexibility and constraint length flexibility. The code rate dictates the number of received bits which are handled together as a symbol at the receiver. Hence, code rate flexibility needs to be built into the basic computing units which are used to implement the Viterbi algorithm. The constraint length dictates the number of computations required per received symbol as well as the manner of transfer of results between these computations. Hence, assuming that multiple processing units are used to perform the required computations, supporting constraint length flexibility necessitates changes in the interconnection network connecting the computing units. A constraint length K Viterbi decoder needs 2K−1computations to be performed per received symbol. The results of the computations are exchanged among the computing units in order to prepare for the next received symbol. The communication pattern according to which these results are exchanged forms a graph called a de Bruijn graph, with 2K−1nodes. This implies that providing constraint length flexibility requires being able to realize de Bruijn graphs of various sizes on the interconnection network connecting the processing units. This thesis focusses on providing constraint length flexibility in an efficient manner. Quite clearly, the topology employed for interconnecting the processing units has a huge effect on the efficiency with which multiple constraint lengths can be supported. This thesis aims to explore the usefulness of interconnection topologies similar to the de Bruijn graph, for building constraint length flexible Viterbi decoders. Five different topologies have been considered in this thesis, which can be discussed under two different headings, as done below: De Bruijn network-based architectures The interconnection network that is of chief interest in this thesis is the de Bruijn interconnection network itself, as it is identical to the communication pattern for a Viterbi decoder of a given constraint length. The problem of realizing flexible constraint length Viterbi decoders using a de Bruijn network has been approached in two different ways. The first is an embedding-theoretic approach where the problem of supporting multiple constraint lengths on a de Bruijn network is seen as a problem of embedding smaller sized de Bruijn graphs on a larger de Bruijn graph. Mathematical manipulations are presented to show that this embedding can generally be accomplished with a maximum dilation of, where N is the number of computing nodes in the physical network, while simultaneously avoiding any congestion of the physical links. In this case, however, the mapping of the decoder states onto the processing nodes is assumed fixed. Another scheme is derived based on a variable assignment of decoder states onto computing nodes, which turns out to be more efficient than the embedding-based approach. For this scheme, the maximum number of cycles per stage is found to be limited to 2 irrespective of the maximum contraint length to be supported. In addition, it is also found to be possible to execute multiple smaller decoders in parallel on the physical network, for smaller constraint lengths. Consequently, post logic-synthesis, this architecture is found to be more area-efficient than the architecture based on the embedding theoretic approach. It is also a more efficiently scalable architecture. Alternative architectures There are several interconnection topologies which are closely connected to the de Bruijn graph, and hence could form attractive alternatives for realizing flexbile constraint length Viterbi decoders. We consider two more topologies from this class -namely, the shuffle-exchange network and the flattened butterfly network. The variable state assignment scheme developed for the de Bruijn network is found to be directly applicable to the shuffle-exchange network. The average number of clock cycles per stage is found to be limited to 4 in this case. This is again independent of the constraint length to be supported. On the flattened butterfly (which is actually identical to the hypercube), a state scheduling scheme similar to that of bitonic sorting is used. This architecture is found to offer the ideal throughput of one decoded bit every clock cycle, for any constraint length. For comparison with a more general purpose topology, we consider a flexible constraint length Viterbi decoder architecture based on a 2D-mesh, which is a popular choice for general purpose applications, as well as many signal processing applications. The state scheduling scheme used here is also similar to that used for bitonic sorting on a mesh. All the alternative architectures are capable of executing multiple smaller decoders in parallel on the larger interconnection network. Inferences Following logic synthesis and power estimation, it is found that the de Bruijn network-based architecture with the variable state assignment scheme yields the lowest (area)−(time) product, while the flattened butterfly network-based architecture yields the lowest (area) - (time)2product. This means, that the de Bruijn network-based architecture is the best choice for moderate throughput applications, while the flattened butterfly network-based architecture is the best choice for high throughput applications. However, as the flattened butterfly network is less scalable in terms of size compared to the de Bruijn network, it can be concluded that among the architectures considered in this thesis, the de Bruijn network-based architecture with the variable state assignment scheme is overall an attractive choice for realizing flexible constraint length Viterbi decoders.

Antenna is an indispensable part of a radar or free space communication system. Antenna requires different stringent specifications for different applications. Designed and fabricated for an intended application, antenna or antenna array has to be evaluated for its far-field characteristics in real free space environment which requires setting up of far-field test site. Maintenance of the site to keep the stray reflections levels low, the cost of the real estate are some of the disadvantages. Nearfield measurements are compact and can be used to test the antennas by exploiting the relationship between near-field and far-field. It is shown that the far-field patterns of an antenna can be sufficiently accurately predicted provided the near-field measurements are accurate. Due to limitation in the near-field measurement systems, errors creep in corrupting the nearfield-measured data thus making error in prediction of the far field. All these errors ultimately corrupt the phase and amplitude data. In this thesis, one such near-field measurement facility, the Planar Near Field Measurement facility is discussed. The limitations of the facility and the errors that occur due to their limitations are discussed. Various errors that occur in measurements ultimately corrupt the near-field phase and amplitude. Investigations carried out aim at a detailed study of these phase and amplitude errors and their effect on the far-field patterns of the antenna. Depending on the source of error, the errors are classified as spike, pulse and random errors. The location of occurrence of these types of errors in the measurement plane, their effects on the far-field of the antenna is studied both for phase and amplitude errors. The studies conducted for various phase and amplitude errors show that the near-field phase and amplitude data are more tolerant to random errors as the far-field patterns do not get affected even for low sidelobe cases. The spike errors, though occur as a wedge at a single point in the measurement plane, have more pronounced effect on the far-field patterns. Lower the taper value of the antenna, more pronounced is the error. It is also noticed that the far-field pattern gets affected only in the plane where the error has occurred and has no effect in the orthogonal plane. Pulse type of errors which occur even for a short length in the measurement affect both the principle plane far-field patterns. This study can be used extensively as a tool to determine to the level to which various error such as mechanical, RF etc need to be controlled to make useful and correct pattern predictions on a particular facility. Thereby, the study can be used as a tool to economise the budget of the facility wherein the parameters required for building the facility need not be over specified beyond the requirement. In general, though this is a limited study, it is certainly a trendsetter in this direction.

TO achieve high level of integration in order to reduce cost, heterodyne architecture has made way for low-IF and zero-IF (direct conversion) receiver architectures. However, a very serious issue in implementing both zero and low-IF receiver is of local oscillator (LO) pulling. Another challenge is on-chip generation of high-precision quadrature LO signals for image-rejection. We have addressed both these issues in this thesis. Regarding the first problem, we have developed a lowpower frequency multiplication technique which uses a low frequency ring oscillator and multiplies its frequency in power e cient way to generate the desired frequency. We then use this differential LO signal to generate high-precision quadrature phases by using polyphase filter and an injection-locked quadrature oscillator. Design examples are presented for 2.4 GHz band of IEEE 802.15.4 standard which is a low-data rate WPAN standard. The standard o ers relaxed performance specifications in order to help achieve low power of operation. Contributions in the thesis • The problem of local oscillator (LO) pulling can be addressed by running LO at a much reduced frequency and use a frequency multiplier (FM) to generate the desired frequency. Also, use of low-frequency LO saves power in VCO and helps eliminate first few dividers leading to significant power savings. In addition, the entire frequency synthesizer can be run at a lower supply voltage saving additional power. The frequency multiplier involves combining edges from the lower frequency ring oscillator. It improves upon the prior work by proposing a new lower-power edge-combiner. The overall power is reduced by exploiting the relaxed phase noise specification of IEEE 802.15.4 standard. Simulations using SpectreRF show that the circuit consumes only 550 ｵW of power in 0.13 ｵm RF-CMOS technology with 1.2 V supply voltage, and provides 950 VP-P sinusoidal output with phase noise of -85.5 dBc/Hz at 1 MHz offset. • An injection-locking based quadrature desensitization circuit is designed for precision quadrature generation. The differential (two phase) output of the frequency multiplier is fed to a polyphase filter to generate nearly quadrature signals. Output of polyphase filter is in turn fed to the desensitizer circuit to obtain high-precision quadrature signals. Designed for 2.4 GHz band in 0.13 µm RF-CMOS technology, it achieves a phase error of 0.5 for 1% mismatch in LC tanks. It achieves a phase noise of -84.3 dBc/Hz at 1 MHz o set and provides quadrature sinusoids of 475 mV amplitude while consuming 1.56 mW of power. • We have analyzed the popular cross-coupled LC-VCOs to generate quadrature sinusoids. In practical LC-oscillators built using low/moderate quality factor on-chip inductors, the actual frequency of oscillation is a little less than 1/2pvLC . This is known as Groszkowski effect. On the other hand, in quadrature oscillator topologies, consisting of two, cross-coupled, negative resistance LC-VCOs using parallel coupling transistors, an upward shift in frequency of oscillation from the free-running frequency of each LC-VCO is observed. This is because in order to satisfy the Barkhausen’s criteria, the LC-tanks have to operate at a frequency away from the frequency of resonance. This e ect called as quadrature detuning effect results in higher phase noise and reduced amplitude. We have shown that the old treatment given in literature is quite inaccurate for practical LC oscillators that are built using low/mo derate Q on-chip inductors. Also the prior work ignores Groszkowski effect which could be significant for low Q LC tanks. We have provided simple, accurate and closed-form expressions of associated frequency-shifts and amplitude of oscillation including both the effects. Our results show excellent match with results obtained from SpectreRF and Matlab simulations.

The development of modern integration technologies is normally driven by the needs of digital CMOS circuit design. Rapid progress in silicon VLSI technologies has made it possible to implement multi-function and high performance electronic circuits on a single die. Coupled with this, the need for interfacing digital blocks to the external world resulted in the integration of analog blocks such as A/D and D/A converters, filters and oscillators with the digital logic on the same die. Thus, mixed signal system-on-chip (SOC) solutions are becoming a common practice in the present day integrated circuit (IC) technologies. In digital domain, aggressive technology scaling redefines, in many ways, the role of interconnects vis-`a-vis the logic in determining the overall performance. Apart from signal integrity, power dissipation and reliability issues, delays over long interconnects far exceeding the logic delay becomes a bottleneck in high speed operation. Moreover, with an increasing density of chips, the number of interchip connections is greatly increased as more and more functions are put on the same chip; thus, the size and performance of the chip are mostly dominated by wiring rather than devices. One of the most promising approaches to solve the above interconnection problems is the use of multiple-valued logic (MVL) inside the chip [Han93, Smi88]. The number of interconnections can be directly reduced with multiple valued signal representation. The reduced complexity of interconnections makes the chip area and delay much smaller leading to reduced cross talk noise and improved reliability. Thus, the inclusion of multiple-valued logic in a otherwise mixed design, consisting of analog and binary logic, can make the transition from analog to digital world much more smoother and at the same time improve the overall system performance. As the sizes of integrated devices decrease, maximum voltage ratings also rapidly decrease. Although decreased supply voltages do not restrict the design of digital circuits, it is harder to design high performance analog and multiple valued integrated circuits using new processes. As an alternative to voltage-mode signal processing, current-mode circuit techniques, which use current as a signal carrier, are drawing strong attention today due to their potential application in the design of high-speed mixed-signal processing circuits in low-voltage standard VLSI CMOS technologies. Industrial interest in this field has been propelled by the proposal of innovative ideas for filters, data converters and IC prototypes in the high frequency range [Tou90, Kol00]. Further, in MVL design using conventional CMOS processing, different current levels can be easily used to represent different logic values. Thus the case for an integrated approach to the design of analog, multi-valued and binary logic circuits using current-mode techniques seems to be worth considering. The work presented in this thesis is an effort to reaffirm the utility of current-mode circuit techniques to some of the existing as well as to some new areas of circuit design. We present new algorithms for the synthesis of a class of analog and multiple-valued logic circuits assuming an underlying CMOS current-mode building blocks. Next we present quaternary current-mode signaling scheme employing a simple encoder and decoder architecture for improving the signal delay characteristics of long interconnects in digital logic blocks. As an interface between analog and digital domain, we present an architecture of current-mode flash A/D converter. Finally, low power being a dominant design constraint in today IC technology, we present a scheme for static power minimization in a class of Current-mode circuits.

This thesis concerns with the recognition of music instruments from isolated notes. Music instrument recognition is a relatively nascent problem fast gaining importance not only because of the academic value the problem provides, but also for the potential it has in being able to realize applications like music content analysis, music transcription etc. Line spectral frequencies are proposed as features for music instrument recognition and shown to perform better than Mel filtered cepstral coefficients and linear prediction cepstral coefficients. Assuming a linear model of sound production, features based on the prediction residual, which represents the excitation signal, is proposed. Four improvements are proposed for classification using Gaussian mixture model (GMM) based classifiers. One of them involves characterizing the regions of overlap between classes in the feature space to improve classification. Applications to music instrument recognition and speaker recognition are shown. An experiment is proposed for discovering the hierarchy in music instrument in a data-driven manner. The hierarchy thus discovered closely corresponds to the hierarchy defined by musicians and experts and therefore shows that the feature space has successfully captured the required features for music instrument characterization.

Network Coding is a technique which looks beyond traditional store-and-forward approach followed by routers and switches in communication networks, and as an extension introduces maps termed as ‘local encoding kernels’ and ‘global encoding kernels’ defined for each communication link in the network. The purpose of both these maps is to define rules as to how to combine the packets input on the node to form a packet going out on an edge. The paradigm of network coding was formally and for the first time introduced by Ahlswede et al. in [1], where they also demonstrated its use in case of single-source multiple-sink network multicast, although with use of much complex mathematical apparatus. In [1], examples of networks are also presented where it is shown that network coding can improve the overall throughput of the network which can not otherwise be realized by the conventional store-and-forward approach. The main result in [1], i.e. the capacity of single-source multiple-sinks information network is nothing but the minimum of the max-flows from source to each sink, was again proved by Li, Yeung, and Cai in [2] where they showed that only linear operations suffice to achieve the capacity of multicast network. The authors in [2] defined generalizations to the multicast problem, which they termed as linear broadcast, linear dispersion, and Generic LCM as strict generalizations of linear multicast, and showed how to build linear network codes for each of these cases. For the case of linear multicast, Koetter and Medard in [3] developed an algebraic framework using tools from algebraic geometry which also proved the multicast max-flow min-cut theorem proved in [1] and [2]. It was shown that if the size of the finite field is bigger than a certain threshold, then there always exists a solution to the linear multicast, provided it is solvable. In other words, a solvable linear multicast always has a solution in any finite field whose cardinality is greater than the threshold value. The framework in [3] also dealt with the general linear network coding problem involving multiple sources and multiple sinks with non-uniform demand functions at the sinks, but did not touched upon the key problem of finding the characteristic(s) of the field in which it may have solution. It was noted in [5] that a solvable network may not have a linear solution at all, and then introduced the notion of general linear network coding, where the authors conjectured that every solvable network must have a general linear solution. This was refuted by Dougherty, Freiling, Zeger in [6], where the authors explicitly constructed example of a solvable network which has no general linear solution, and also networks which have solution in a finite field of char 2, and not in any other finite field. But an algorithm to find the characteristic of the field in which a scalar or general linear solution(if at all) exists did not find any mention in [3] or [6]. It was a simultaneous discovery by us(as part of this thesis) as well as by Dougherty, Freiling, Zeger in [7] to determine the characteristics algorithmically. Applications of Network Coding techniques to wireless networks are seen in literature( [8], [9], [10]), where [8] provided a variant of max-flow min-cut theorem for wireless networks in the form of linear programming constraints. A new architecture termed as COPE was introduced in [10] which used opportunistic listening and opportunistic coding in wireless mesh networks.