4 mal im Jahr erscheinende Zeitschrift über aktuelle Themen der TU Chemnitz:Ein Pakt für mehr Planungssicherheit ist dringend nötig Verhüllter Nischel Auf der Suche nach dem größten gemeinsamen Nenner Das Studium mit der Maus Internationalisierung kontra Drittklassigkeit Ein toller Service für Erfinder Uni-Teil Erfenschlag bald nicht mehr am Ende der Welt Auf nach Sachsen Die Chemnitzer Ost- und Mitteleuropaexperten Mit Vollgas zum Diplom Die Profs sind Sahne Rasante Abfahrten und peitschender Regen Bildung macht um neue Medien keinen Bogen Von Carbon bis Alaska Leichter, fester, besser Schicker Look fürs Handgelenk Doping mit Carbon Kugelsicher auf vier Rädern Alles fließt Licht misst Wasser So brennt die Kohle besser Damit nicht nur Gras darüber wächst Fehler im System Damit der Fensterheber nicht spinnt Der kleine Lauschangriff an der Zapfsäule Schnittmenge im Hightech-Bereich Der tanzende Roboter Die Wirklichkeit als Vorlage Der Geigenkasten aus Mutter Natur Damit die Energie verlustarm zum Kunden kommt Der beeindruckte Bundeskanzler Per Mausklick ins entsaubte Empire Ein großes Projekt für winzige Teile Eine virtuelle Reise in die Fabrik der Zukunft Neue Funken in der Ideenschmiede für Politiker Nachwuchs in der Technikwissenschaftlichen Klasse Per Simulation zur flexiblen Fabrik Hier werden Zeichen gesetzt Träumen im Viervierteltakt Ein gelungener Brückenschlag nach Tschechien Mehr als eine Sternschnuppe in der Orangerie 191 junge Forscher entdeckten Chemnitz Konzepte lassen sich nicht einfach kopieren Aktienmarkt und Luftverkehr - ein Fass ohne Boden? Giraffen kann es nicht geben Jubel über Rückkehr in die 2. Bundesliga Abdrücken ist einfach - Zielen ist schwieriger

It is a great research interest to integrate the Cell/B.E. processor into an AMD Opteron system. The result is a system benefiting from the advantages of both processors: the high computational power of the Cell/B.E. and the high I/O throughput of the Opteron. The task of this diploma thesis is to accomplish, that Cell-SPU code initially residing on the Opteron could be executed on the Cell under the GNU/Linux operating system. However, the SPUFS (Synergistic Processing Unit File System), provided from STI (Sony, Toshiba, IBM), does exactly the same thing on the Cell. The Cell is a combination of a PowerPC core and Synergistic Processing elements (SPE). The main work is to analyze the SPUFS and migrate it to the Opteron System. The result of the migration is a project called RSPUFS (Remote Synergistic Processing Unit File System), which provides nearly the same interface as SPUFS on the Cell side. The differences are caused by the TCP/IP link between Opteron and Cell, where no Remote Direct Memory Access (RDMA) is available. So it is not possible to write synchronously to the local store of the SPEs. The synchronization occurs implicitly before executing the Cell-SPU code. But not only semantics have changed: to access the XDR memory RSPUFS extends SPUFS with a special XDR interface, where the application can map the XDR into the local address space. The application must be aware of synchronization with an explicit call of the provided ''xdr\_sync'' routine. Another difference is, that RSPUFS does not support the gang principle of SPUFS, which is necessary to set the affinity between the SPEs. This thesis deals not only with the operating system part, but also with a library called ''libspe''. Libspe provides a wrapper around the SPUFS system calls. It is essential to port this library to the Opteron, because most of the Cell applications use it. Libspe is not only a wrapper, it saves a lot of work for the developer as well, like loading the Cell-SPU code or managing the context and system calls initiated by the SPE. Thus it has to be ported, too. The result of the work is, that an application can link against the modified libspe on the Opteron gaining direct access to the Synergistic Processor Elements.

This dissertation presents the results of research towards a new computer architectural approach for the construction of digital signal processors. The new approach is based on a transport triggered architecture (TTA) and allows for a dataflow processing mode. The proposed architecture has beed called TAD (Transport triggered Architecture with Dataflow-extension). The designed machine is able to execute limited dataflow-graphs using a single assembly instruction. The size of the dataflow-graph is limited by the number of available execution units and communication resources. To undertake the research a cycle-correct simulator of the proposed microarchitecture has been designed. Benchmark results of the new microarchitecture were obtained by executing typical DSP-programs on the simulator. The properties of the new architecture and the variants of its parameters are discussed in the text. i Performance data is given on a per-cycle basis. A demonstration machine for the TAD has been synthesized for a 0.35um CMOS-technology. Data for area and maximum clock frequency of the design have been extracted from the routed chip design. / Diese Arbeit stellt die Ergebnisse von Untersuchungen über eine neue Architekturvariante für digitale Signalverarbeitungsprozessoren mit transportgesteuerter Architektur (TTA) vor. Die dazu entworfene Maschine erlaubt es, endliche Datenflussgraphen auf einen einzelnen Maschinenbefehl abzubilden. Die maximale Größe der abbildbaren Datenflussgraphen ist dabei durch die Anzahl gleichzeitig verfügbarer Verarbeitungseinheiten und Kommunikationsresourcen beschränkt. Die Untersuchungen dazu wurden mit einem taktgenauen Mikroarchitektursimulator durchgeführt. Die Daten zur Verarbeitungsleistung der Maschine wurden durch das Ausführen von Lastprogrammen auf diesem Simulator gewonnen. Der Aufbau und die Eigenschaften der durch den Simulator realisierten Mikroarchitektur und einige von dieser Implementation abweichende Varianten werden erläutert. Da sich Angaben zur Anzahl der Verarbeitungszyklen nicht vergleichen lassen, ohne dass Informationen zur maximal erreichbaren Taktfrequenz der Implementation vorliegen, wurde die vorgeschlagene Mikroarchitektur als integrierter Schaltkreis synthetisiert, um Informationen zu Flächenbedarf und Laufzeit zu gewinnen. Aus den Entwurfsdaten für den integrierten Schaltkreis wurden die Verdrahtungs-Kapazitäten extrahiert und daraus die Information zur maximalen Taktfrequenz gewonnen.

Microprocessors have experienced a significant stall in single-thread performance since about 2004. Instead of significant annual performance improvements for a single core, it is easier to increase performance by providing multiple, independent cores that the application programmer has to coordinate. Exposing concurrency to the applications requires mechanisms to control it. Hardware Transactional Memory (HTM) is an abstraction that provides optimistic, fine-grained concurrency control with a simple application interface, and has received significant research attentions fro 2004 - 2010, with initial publications in the mid-90s. The central thesis of my work is that detailed analysis and ISA modelling of HTM is necessary to understand actual implementation and usage challenges, and get more realistic results. Instead of overly complicating the design of HTM with features that would be extremely hard to implement right in a more detailed microarchitecture and ISA proposal, I suggest that getting a base-line HTM specification and micro-architecture right is a challenge in itself. Yet, despite the complexity, there are interesting implementation options and extensions that can provide benefits to applications using HTM–but they are not on the trajectory taken by most papers published between 2004 and 2010.

Shared microarchitectural state is a target for side-channel attacks that leverage timing measurements to leak information across security domains. These attacks are further enhanced by speculative execution, which transiently distorts the control and data flow of applications, and by untrusted environments, where the attacker may have complete control over the victim program. Under these conditions, microarchitectural attacks can bypass software isolation mechanisms, and hence they threaten the security of virtually any application running in a shared environment. Numerous approaches have been proposed to defend against microarchitectural attacks, but we lack the means to test them and ensure their effectiveness. The users cannot test them manually because the effects of the defences are not visible to software. Testing the defences by attempting attacks is also suboptimal because the attacks are inherently unstable, and a failed attack is not always an indicator of a successful defence. Moreover, some classes of defences can be disabled at runtime. Hence, we need automated tools that would check the effectiveness of defences, both at design time and at runtime. Yet, as it is common in security, the existing solutions lag behind the developments in attacks. In this thesis, we propose three techniques that check the effectiveness of defences against modern microarchitectural attacks. Revizor is an approach to automatically detect microarchitectural information leakage in commercial black-box CPUs. SpecFuzz is a technique for dynamic testing of applications to find instances of speculative vulnerabilities. Varys is an approach to runtime monitoring of system defences against microarchitectural attacks. We show that with these techniques, we can successfully detect microarchitectural vulnerabilities in hardware and flaws in defences against them; find unpatched instances of speculative vulnerabilities in software; and detect attempts to invalidate system defences.