Zugl.: Vallendar, WHU - Otto Beisheim School of Management, Diss., 2007

Many controller tuners are based on linear models of both the controller and process. Desired performance is often predetermined or adjusted in a manner which is not directly related to the desired response. All physical processes contain nonlinearities, commonly of the actuator saturating type, and many controllers contain heuristics for implementation in real systems, such as anti-integral wind up in PID controllers. For different processes a range of closed loop response shapes are desired, often described by features of the response such as rise time, overshoot and settling time. This thesis investigates the possibility of basing controller tuning on closed loop system response data such that desired performance is incorporated directly in terms of familiar time domain features or labels thus eliminating the need for a mathematical process model and repeated tuning reformulations to achieve the desired performance. A controller tuning method named Label Based Neuro-Control is developed and analysed by application to PID controller tuning for a number of process models indicative of real process behaviour. The Method of Inequalities is employed as a comparative controller tuning technique and observations are made concerning its performance. Simulations and numerical investigation indicate that LBNC is a viable technique for the tuning of low order controllers for SISO processes. Tuning is straightforward, flexible and copes well with process parametric changes and performance specification reformulation. The drawbacks are a complicated pretune phase, a limited selection of suitable labels and a difficulty in defining general classes of tuning problems for its application. The method of inequalities is shown to be a powerful technique applicable to higher order controllers and provides a natural incorporation of system constraints. However, operator supervision is necessary for successful tuning. Neither technique is based on the assumption of process linearity but due to the inability to characterise classes of input signals and operating points the types of process nonlinearity are restricted. The controller may be nonlinear, but must be predetermined, and an input/output process model of arbitrary structure is required.

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Made available in DSpace on 2014-06-12T17:35:31Z (GMT). No. of bitstreams: 2 arquivo2601_1.pdf: 857611 bytes, checksum: e309a15babbf5fe7653340a2b28afd9f (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2011 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / O gerenciamento dos negócios possibilita o gestor reunir informações que lhe propicie o planejamento, controle e tomada de decisões, inclusive em eventos futuros da mutação patrimonial da entidade. Dentro deste contexto, o presente estudo teve como objetivo analisar o atual perfil profissional de competências e habilidades exigidas pelas empresas contratantes para a função de controller, bem como investigar se o perfil desejado para este profissional tem associação ao porte da empresa, a sua origem de capital, a hierarquia do cargo, formação acadêmica e salário ofertado pelo atual mercado de trabalho. Para isto, buscou-se identificar os requisitos exigidos pelas organizações contratantes, através dos anúncios de seleção e recrutamento on line nos sites das empresas Catho, Manager, Michel Page e Rhobert Half no período de abril a agosto de 2010. Foram utilizados 295 anúncios válidos e as informações foram tratadas com análise de conteúdo, analisadas descritivamente e estatisticamente com auxílio do software Statistical Package of The Social Sciences (SPSS), versão 16.0. As variáveis foram analisadas quanto à associação estatisticamente significativa em relação ao porte da empresa, a origem do capital, a hierarquia do cargo e formação acadêmica e salário ofertado. Os dados foram organizados em perfil técnico, perfil de gestão e perfil comportamental além de identificar os benefícios oferecidos pelas empresas. A faixa salarial de maior percentual válido foi para salários a partir de R$ 8.000,00 com aproximadamente 50% das vagas. Os resultados apresentaram associação estatística significativa entre o perfil comportamental e o porte da empresa e a origem de capital, entre o perfil técnico e a hierarquia do cargo e também entre os benefícios oferecidos e o porte da empresa

Advanced development in processor design, increasing the heterogeneity of computer system, by involving Graphics Processing Units (GPUs), Field-Programmable Gate Arrays (FPGAs) and custom accelerators, and increasing the number of cores and threads in such systems puts extra pressure on the main memory, demanding a higher performance. Current computing trends are putting ever more pressure on main memory. In modern computer systems, this is generally Dynamic Random Access Memory (DRAM) which consists of a multi-level access hierarchy (e.g. Rank, Bank, Row etc.). This heterogeneity of structure implies different access latencies (and power consumption), resulting in performance differences according to memory access patterns. DRAM controllers manage access and satisfy the timing constraints and now employ complex scheduling and prediction algorithms to mitigate the effect on performance. This complexity can limit the scalability of a controller with the size of memory, while maintaining performance. The focus of this PhD thesis is to improve performance, reliability and scalability (with respect to memory size) of DRAM controllers. To this end, it covers three significant contributors to the performance and reliability of a memory controller: ‘Address Mapping’, ‘Page Closure Policies’ and ‘Reliability Monitoring’. A detailed DRAM simulator is used as an evaluation platform throughout this work. The following contributions are presented in this thesis. Hybrid Address-based Page PolicY (HAPPY): Memory controllers have used static page-closure policies to decide whether a row should be left open (open-page policy) or closed immediately (close-page policy) after use. The appropriate choice can reduce the average memory latency. Since access patterns are dynamic, static page policies cannot guarantee to deliver optimum execution time. Hybrid page policies can cover dynamic scenarios and are now implemented in state-of-the-art processors. These switch between open-page and close-page policies by monitoring the access pattern of row hits/conflicts and predicting future behaviour. Unfortunately, as the size of DRAM memory increases, fine-grain tracking and analysis of accesses does not remain practical. HAPPY proposes a compact, memory address-based encoding technique which can maintain or improve page closure predictor performance while reducing the hardware overhead. As a case study, HAPPY is integrated, with a state-of-the-art monitor – the Intel-adaptive open-page policy predictor employed by the Intel Xeon X5650 – and a traditional Hybrid page policy. The experimental results show that using the HAPPY encoding applied to the Intel-adaptive page closure policy can reduce the hardware overhead by 5× for the evaluated 64 GB memory (up to 40× for a 512 GB memory) while maintaining the prediction accuracy. Dynamic Re-arrangement of Address Mapping (DReAM): The initial location of data in DRAMs is determined and controlled by the ‘address-mapping’ and even modern memory controllers use a fixed and runtime-agnostic address-mapping. On the other hand, the memory access pattern seen at the memory interface level will be dynamically changed at run-time. This dynamic nature of memory access pattern and the fixed behaviour of address mapping process in DRAM controllers, implied by using a fixed address-mapping scheme, means that DRAM performance cannot be exploited efficiently. DReAM is a novel hardware technique that can detect a workload-specific address mapping at run-time based on the application access pattern. The experimental results show that DReAM outperforms the best evaluated baseline address mapping by 5%, on average, and up to 28% across all the workloads. A Run-time Memory hot-row detectOR (ARMOR): DRAM needs refreshing to avoid data loss. Data can also be corrupted within a refresh interval by crosstalk caused by repeated accesses to neighbouring rows; this is the row hammer effect and is perceived as a potentially serious reliability and security threat. ARMOR is a novel technique which improves memory reliability by detecting which rows are potentially being “hammered” within the memory controller, which can then insert extra refresh operations. It can detect (and thus prevent) row hammer errors with minimal execution time overhead and hardware requirements. Alternatively by adding buffers inside the memory controller to cache such hammered rows, execution times are reduced with small hardware costs. The ARMOR technique is now the basis of a patent applicant and under process for commercial exploitation. As a final step of this PhD thesis, an adaptive memory controller was developed integrating HAPPY, DReAM and ARMOR into a standard memory controller. The performance and the implementation cost of such an adaptive memory controller were compared against a state-of-the-art memory controller, as a baseline. The experimental results show that the adaptive memory controller outperforms the baseline, on average by 18%, and up to 35% for some workloads, while requiring around 6 KB-900 KB more storage than the baseline to support a wide range of memory sizes (from 4 GB up to 512 GB).

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This thesis describes a system to allow a mass storage device to be installed in a position remote from the computer system which controls it. This system is intended to allow undergraduate students in the Electrical Engineering department at UCT to make use of two nine channel tape drives installed in the undergraduate interfaced to accessed by laboratory for project work. The drives are the department's PDP-11/23 computer, and may be standard operating system directives, as the controller simulates a conventional computer peripheral. The system consists of an SA-Bus based tape transport controller which interfaces to the host computer system via a serial line. The following hardware was designed and built specifically for this system : 1. A CPU card based on the in Tel 80188 microprocessor, incorporating high speed DMA (direct memory access) channels and two interrupt driven serial lines. 2. A timing and control module for the tape transports. This consists of two SA-Bus cards. Two sets of software were written for the system. These are the following : 1. Software to operate the tape controller. This consists of six modules written in Pascal-86 and 8086 assemblers. 2. Software to allow the PDP-11/23 to control the tape drives. This is in the. form of an RSX-11 device driver written in PDP-11 assembler. To allow the particular to proposed local system allow area highly modular form. to be easily the system to network) , the upgraded in the future (in be incorporated into UCT's software was written in an addition to being controlled by a host system in remote mode the tape controller also has the ability to perform a variety of operations in local mode. These include the ability to copy and erase tapes, as well as a comprehensive set of diagnostic functions. When in local operations mode the controller is menu driven, making its use by persons who are not familiar with it quick and easy.

Vi har i denna kvalitativa studie med induktiv ansats genomfört två fallstudier med syfte attstudera skillnaderna mellan den funktionella eller formaliserade definitionen av controllern frånden praktiska och handlingsorienterade definitionen. Samtidigt studerade vi skillnaderna mellancontrollerns syn på sin egen roll och controllerns kollegors syn på dess roll. Analysen hargenomförts med hjälp av en teoretisk referensram som vi byggt upp utifrån två kategorier sompåverkar controllerns roll, interna samt externa faktorer. Det vi kommit fram till visar att detfinns tydliga skillnader mellan den funktionella eller formaliserade definitionen från denpraktiska och handlingsorienterade definitionen. Vidare resultat som framkommit genom vårstudie är att controllern idag närmar sig ledningen och de klassiska arbetsuppgifterna tas allt meröver av datorer och ekonomisystem, vilket är den största skillnaden som framkommit från denfunktionella definitionen som litteraturen ger oss. Ytterligare har vi kommit fram till att deinterna faktorerna påverkar controllerns roll i den mån som de externa faktorerna tillåter dem.Till sist kom vi även fram till att det finns skillnader mellan controllerns syn på sin egen roll ochderas kollegors syn på controllerns roll. Den största orsaken till denna skillnad anser vi är att allaindivider ser på saker ur olika perspektiv och ser därmed olika på olika situationer. Syftet medstudien är att belysa om skillnaderna i de två olika frågeställningarna finns. Vi har kommit framtill att skillnaderna finns, således anser vi att studiens syfte har uppfyllts. / Program: Civilekonomprogrammet