Security and reliability in processor based systems are concerns requiring adroit solutions. Security is often compromised by code injection attacks, jeopardizing even ???trusted software???. Reliability is of concern, where unintended code is executed in modern processors with ever smaller feature sizes and low voltage swings causing bit flips. Countermeasures by software-only approaches increase code size and therefore significantly reduce performance. Hardware assisted approaches use additional hardware monitors and thus incur considerably high hardware cost and have scalability problems. Considering reliability and security issues during the design of an embedded system has its advantages as this overcomes the limitations of existing solutions. The research work presented in this thesis combines two elements: one, defining a hardware software design framework for reliability and security monitoring at the granularity of micro-instructions, and two, applying this framework for real world problems. At a given time, a processor executes only a few instructions and large part of the processor is idle. Utilizing these idling hardware components by sharing them with the monitoring hardware, to perform security and reliability monitoring reduces the impact of the monitors on hardware cost. Using micro-instruction routines within the machine instructions, allows us to share most of the monitoring hardware. Therefore, our technique requires little hardware overhead in comparison to having additional hardware blocks outside the processor. This reduction in overhead is due to maximal sharing of hardware resources of the processor. Our framework is superior to software-only techniques as the monitoring routines are formed with micro-instructions and therefore reduces code size and execution time overheads, since they occur in parallel with machine instructions. This dissertation makes four significant contributions to the field of security and reliability on embedded processor research and they are: (i) proposed a security and reliability framework for embedded processors that could be included into its design phase; (ii) shown that inline (machine instruction level) monitoring will detect common security attacks (four inline monitors against common attacks cost 9.21% area and 0.67% performance, as opposed to previous work where an external monitor with two monitoring modules costs 15% area overhead); (iii) illustrated that basic block check-summing for code integrity is much simpler and efficient than currently proposed integrity violation detectors which address code injection attacks (this costs 5.03% area increase and 3.67% performance penalty with a single level control flow checking, as opposed to previous work where the area overhead is 5.59%, which needed three control flow levels of integrity checking); and (iv) shown that hardware assisted control flow checking implemented during the design of a processor is much cheaper and effective than software only approaches (this approach costs 0.24-1.47% performance and 3.59% area overheads, as opposed to previous work that costs 53.5-99.5% performance).

No description available.

A new hardware system for the ECE 4550 Control System Design lab is proposed. The current hardware is examined and its shortcomings are documented. Design guidelines for the new system are put forth and interfaces between hardware elements are defined. Four hardware elements are developed: a motherboard, an I/O daughtercard, a DC motor driver daughtercard, and an AC motor driver daughtercard. Each of these systems is examined in depth from a design decision standpoint as well as from the standpoint of the design guidelines promulgated earlier. Technical limitations for each system are disclosed and examined in detail.

Thesis (M.S.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

Security and reliability in processor based systems are concerns requiring adroit solutions. Security is often compromised by code injection attacks, jeopardizing even ???trusted software???. Reliability is of concern, where unintended code is executed in modern processors with ever smaller feature sizes and low voltage swings causing bit flips. Countermeasures by software-only approaches increase code size and therefore significantly reduce performance. Hardware assisted approaches use additional hardware monitors and thus incur considerably high hardware cost and have scalability problems. Considering reliability and security issues during the design of an embedded system has its advantages as this overcomes the limitations of existing solutions. The research work presented in this thesis combines two elements: one, defining a hardware software design framework for reliability and security monitoring at the granularity of micro-instructions, and two, applying this framework for real world problems. At a given time, a processor executes only a few instructions and large part of the processor is idle. Utilizing these idling hardware components by sharing them with the monitoring hardware, to perform security and reliability monitoring reduces the impact of the monitors on hardware cost. Using micro-instruction routines within the machine instructions, allows us to share most of the monitoring hardware. Therefore, our technique requires little hardware overhead in comparison to having additional hardware blocks outside the processor. This reduction in overhead is due to maximal sharing of hardware resources of the processor. Our framework is superior to software-only techniques as the monitoring routines are formed with micro-instructions and therefore reduces code size and execution time overheads, since they occur in parallel with machine instructions. This dissertation makes four significant contributions to the field of security and reliability on embedded processor research and they are: (i) proposed a security and reliability framework for embedded processors that could be included into its design phase; (ii) shown that inline (machine instruction level) monitoring will detect common security attacks (four inline monitors against common attacks cost 9.21% area and 0.67% performance, as opposed to previous work where an external monitor with two monitoring modules costs 15% area overhead); (iii) illustrated that basic block check-summing for code integrity is much simpler and efficient than currently proposed integrity violation detectors which address code injection attacks (this costs 5.03% area increase and 3.67% performance penalty with a single level control flow checking, as opposed to previous work where the area overhead is 5.59%, which needed three control flow levels of integrity checking); and (iv) shown that hardware assisted control flow checking implemented during the design of a processor is much cheaper and effective than software only approaches (this approach costs 0.24-1.47% performance and 3.59% area overheads, as opposed to previous work that costs 53.5-99.5% performance).

Técnicas que partem de modelos de alto nível de abstração são requeridas para lidar com a complexidade encontrada nas novas gerações de sistemas embarcados, sendo cruciais para o sucesso do projeto. Uma grande redução do esforço pode ser obtida com o uso de modelos quando código em uma linguagem de programação pode ser gerado automaticamente a partir desses. Porém, ferramentas disponíveis para modelagem e geração de código normalmente são dependentes de domínio e o software embarcado normalmente possui comportamento heterogêneo, requerendo suporte a múltiplos modelos de computação. Nesta tese, estratégias para desenvolvimento de software embarcado baseado em modelos de alto nível usando UML e Simulink são analisadas. A partir desta análise, observaram-se as principais limitações das abordagens para geração de código baseadas em UML e Simulink. Esta tese, então, propõe estratégias para melhorar a automação provida por estas ferramentas, como por exemplo, propondo uma abordagem para geração de código multithread a partir de modelos Simulink. A comparação feita entre UML e Simulink mostra que, embora UML seja a linguagem mais usada no domínio de engenharia de software, UML é baseada em eventos e não é adequada para modelar sistemas dataflow. Por outro lado, Simulink é largamente usado por engenheiros de hardware e de controle, além de suportar dataflow e geração de código. Porém, Simulink provê abstrações de mais baixo nível, quando comparado a UML. Conclui-se que tanto UML como Simulink possuem prós e contras, o que motiva a integração de ambas linguagens em um único fluxo de projeto. Neste contexto, esta tese propõe também uma abordagem integradora para desenvolvimento de software embarcado que inicia com uma especificação de alto nível descrita usando diagramas UML, a partir da qual modelos dataflow e control-flow podem ser gerados. Desta maneira, o modelo UML pode ser usado como front-end para diferentes abordagens de geração de código, incluindo UML e a proposta geração de código multithread a partir de modelos Simulink. / The use of techniques starting from higher abstraction levels is required to cope with the complexity that is found in the new generations of embedded systems, being crucial to the design success. A large reduction of design effort when using models in the development can be achieved when there is a possibility to automatically generate code from them. Using these techniques, the designer specifies the system model using some abstraction and code in a programming language is generated from that. However, available tools for modeling and code generation are domain-specific and embedded software usually shows heterogeneous behavior, which pushes the need for supporting software automation under different models of computation. In this thesis, strategies for embedded software development based on high-level models using UML and Simulink were analyzed. We observed that the embedded software generation approaches based on UML and Simulink have limitations, and hence this thesis proposes strategies to improve the automation provided on those approaches, for example, proposing a Simulink-based multithread code generation. UML is a well used language in the software engineering domain, and we consider that it has several advantages. However, UML is event-based and not suitable to model dataflow systems. On the other side, Simulink is widely used by control and hardware engineers and supports dataflow, and time-continuous models. Moreover, tools are available to generate code from a Simulink model. However, Simulink models represent lower abstraction level compared to UML ones. This comparison shows that UML and Simulink have pros and cons, which motivates the integration of both languages in a single design process. As the main contribution, we propose in this thesis an integrated approach to embedded software design, which starts from a high-level specification using UML diagrams. Both dataflow and control-flow models can be generated from that. In this way, an UML model can be used as front-end for different code generation approaches, including UML-based one and the proposed Simulink-based multithread code generation.

Técnicas que partem de modelos de alto nível de abstração são requeridas para lidar com a complexidade encontrada nas novas gerações de sistemas embarcados, sendo cruciais para o sucesso do projeto. Uma grande redução do esforço pode ser obtida com o uso de modelos quando código em uma linguagem de programação pode ser gerado automaticamente a partir desses. Porém, ferramentas disponíveis para modelagem e geração de código normalmente são dependentes de domínio e o software embarcado normalmente possui comportamento heterogêneo, requerendo suporte a múltiplos modelos de computação. Nesta tese, estratégias para desenvolvimento de software embarcado baseado em modelos de alto nível usando UML e Simulink são analisadas. A partir desta análise, observaram-se as principais limitações das abordagens para geração de código baseadas em UML e Simulink. Esta tese, então, propõe estratégias para melhorar a automação provida por estas ferramentas, como por exemplo, propondo uma abordagem para geração de código multithread a partir de modelos Simulink. A comparação feita entre UML e Simulink mostra que, embora UML seja a linguagem mais usada no domínio de engenharia de software, UML é baseada em eventos e não é adequada para modelar sistemas dataflow. Por outro lado, Simulink é largamente usado por engenheiros de hardware e de controle, além de suportar dataflow e geração de código. Porém, Simulink provê abstrações de mais baixo nível, quando comparado a UML. Conclui-se que tanto UML como Simulink possuem prós e contras, o que motiva a integração de ambas linguagens em um único fluxo de projeto. Neste contexto, esta tese propõe também uma abordagem integradora para desenvolvimento de software embarcado que inicia com uma especificação de alto nível descrita usando diagramas UML, a partir da qual modelos dataflow e control-flow podem ser gerados. Desta maneira, o modelo UML pode ser usado como front-end para diferentes abordagens de geração de código, incluindo UML e a proposta geração de código multithread a partir de modelos Simulink. / The use of techniques starting from higher abstraction levels is required to cope with the complexity that is found in the new generations of embedded systems, being crucial to the design success. A large reduction of design effort when using models in the development can be achieved when there is a possibility to automatically generate code from them. Using these techniques, the designer specifies the system model using some abstraction and code in a programming language is generated from that. However, available tools for modeling and code generation are domain-specific and embedded software usually shows heterogeneous behavior, which pushes the need for supporting software automation under different models of computation. In this thesis, strategies for embedded software development based on high-level models using UML and Simulink were analyzed. We observed that the embedded software generation approaches based on UML and Simulink have limitations, and hence this thesis proposes strategies to improve the automation provided on those approaches, for example, proposing a Simulink-based multithread code generation. UML is a well used language in the software engineering domain, and we consider that it has several advantages. However, UML is event-based and not suitable to model dataflow systems. On the other side, Simulink is widely used by control and hardware engineers and supports dataflow, and time-continuous models. Moreover, tools are available to generate code from a Simulink model. However, Simulink models represent lower abstraction level compared to UML ones. This comparison shows that UML and Simulink have pros and cons, which motivates the integration of both languages in a single design process. As the main contribution, we propose in this thesis an integrated approach to embedded software design, which starts from a high-level specification using UML diagrams. Both dataflow and control-flow models can be generated from that. In this way, an UML model can be used as front-end for different code generation approaches, including UML-based one and the proposed Simulink-based multithread code generation.

The thesis discusses the possible ways of remote management of devices running Mikrotik RouterOS and choosing appropriate variant for implementation of automated remote management of the device, which is part of a mobile robot. Due to the limited capabilities of embedded system, from which it is necessary to perform automated remote management of device with this operating system, it was not possible to use standardized protocols for this purpose. A substantial part of this work therefore deals with analysis and detailed documentation of proprietary protocols implemented in the MikroTik RouterOS operating system, which are suitable for implementation in an embedded system, from which it is necessary to perform automated remote management. The conclusion describes the principle of the proposed and realized implementation of proprietary protocols in C language. The described implementation is part of the library, which provides automated remote management using these protocols.

This report is about the evaluation of different microcontrollers and their current con-sumption, specifically microcontrollers that will run AI models. The company Sensorbeeneeds a new microcontroller for their future projects. One of the areas of use will be AImodels. The most important parameter for Sensorbee is current consumption, minimizingcurrent consumption is a top priority as their products are powered by batteries or solarpanels. At the beginning of the project, the focus was on which microcontroller had thelowest current consumption. For AI models in particular, however, it turned out to be avery big difference in the optimization of the software. A well-optimized AI model canquickly classify data, which in turn leads to the microcontroller being able to spend muchof its time in sleep mode. This meant that not only the current consumption of the micro-controller could be taken into account, but how fast it ran through an AI model was at leastas important, if not more important. Even how easy it was for Sensorbee to get startedwith the new processor had to be evaluated, as Sensorbee is a small company that has littleresources to move around with. The candidate that was most promising in the beginningproved to be useless as the performance of the AI model was too poor and the general sup-port for the microcontroller was unsatisfactory. It turns out that there are a lot of variablesto consider when choosing a microcontroller and not just what is in the datasheet.

In the field of embedded systems, computers embedded into machines ranging from microwaveovensto assembly lines impact the physical world. They do so under tight real-time constraintswith ever-increasing demand for computing power and performance. Development of higher speedprocessors have been hampered by diminishing returns on power consumption as clock frequency isfurther increased. For this reason, today, embedded processor development is instead moving towardfurther concurrency with multi-core processors being considered more and more every day. Withparallelism comes challenges, such as interference caused by shared resources. Contention betweenprocessor cores, such as shared memory, result in inter-core interference which is potentially unpredictableand unbounded. The focus of this thesis is placed on minimizing inter-core interferencewhile meeting local task timing requirements by utilizing scheduling heuristics. A scheduling heuristicis designed and a prototype scheduler which implements this algorithm is developed. Thescheduler is evaluated on randomly generated test cases, where its ability to keep inter-core datapropagationdelays low across different core counts and utilization values was evaluated. The algorithmis also compared with constraint programming in a real world industrial test case. Theobtained results show that the algorithm can produce schedules with low inter-core delays in a veryshort time, although not being able to optimize them fully compared to constraint programming.