Thesis (Ph. D.)--University of Missouri-Columbia, 1998. / Wanting leaves 220-226 Conclusions and recommendations. Typescript. Vita. Includes bibliographical references (leaves [339]-342). Also available on the Internet.

Thesis (Ph.D.)--Ohio University, August, 2006. / Title from PDF t.p. Includes bibliographical references.

This thesis presents the theory, analysis, testing and implementation of a scheme to reduce shunt compensation capacitor switching transients. The described method is switch the capacitors very near the instant when the bus voltage is at a power frequency zero. This was accomplished with a vacuum breaker on a 230 kV shunt capacitor bank.

Switch level faults, as opposed to traditional gate level faults, can more accurately model physical faults found in an integrated circuit. However, existing fault simulation techniques have a worst-case computational complexity of O(n²), where n is the number of devices in the circuit. This paper presents a novel switch level extension to parallel fault simulation and the switch level circuit partitioning needed for parallel processing. The parallel switch level fault simulation technique uses 9-valued logic, N and P-type switch state tables, and a minimum operation in order to simulate all faults in parallel for one switch. The circuit partitioning method uses reverse level ordering, grouping, and subgrouping in order to partition transistors for parallel processing. This paper also presents an algorithm and complexity measure for parallel fault simulation as extended to the switch level. For the algorithm, the switch level fault simulation complexity is reduced to O(L²), where L is the number of levels of switches encountered when traversing from the output to the input. The complexity of the proposed algorithm is much less than that for traditional fault simulation techniques. / Ph. D.

M. Tech. Electrical Engineering / Investigates the reasons behind the poor performance of distance relays on series compensated lines. In order to achieve this objective, a case study will be established in a power system software (DigSilent Power Factory). Furthermore, a practical incident that occurred on Eskom's compensated network will be examined. However, prior to investigating the performance of the distance relay on transmission lines, there are some other critical aspects that have to be thoroughly understood. These aspects include amongst others: transmission line modelling ; numeric relay algorithms ; distance protection philosophies ; series compensation phenomena ; analysis of distance relays performance on both compensated and uncompensated lines and the action and influence of the MOV. The study will provide a better understanding regarding the dynamic behaviour of the impedance protection relay under fault conditions on series compensated lines and the behaviour of the MOV during a fault.

M. Tech. Electrical Engineering / Investigates the growing consensus that significant advantages can be achieved through the automation of distribution feeder switches In order to ensure quality and reliability of supply to single phase consumers by electrical utilities, a need arose to minimize unbalance. it is then postulated the unbalance due to uneven distribution of single-phase loads at the secondary side of the distribution network can be minimized using automatic and remote sensing technology.

Low-voltage switchgear and controlgear assemblies with a rated short-circuit withstand strength above 10 kA, are required, by law, to conform to the South African standard, SANS 1473-1 (Low Voltage Switchgear and Controlgear Assemblies: Part 1: Typetested, partially type-tested and specially tested assemblies with rated short-circuit withstand strength above lOkA). Standard SANS 1473-1 stipulates three categories of assemblies i.e. type-tested, partially type-tested and specially tested assemblies. The specially tested assembly is unique to the South African market, while the other two categories are stipulated in standard SANS IEC 60439-1 (Low Voltage Switchgear and Controlgear Assemblies: Part 1: Type-tested and partially type-tested assemblies), which is internationally accepted in many countries as the applicable low-voltage assembly standard. Standard SANS 1473-1 specifies seven type-tests for certification as a type-tested assembly (TTA), but specifies, at most, three type-tests for certification as a specially tested assembly (STA). The underlying purpose of a technical standard is to provide for the safety of people and property, with the purpose of the research being twofold: 1. To investigate if the testing requirements specified for a specially tested assembly (STA), in accordance with standard SANS 1473-1, are correctly applied, and do not pose any safety risks. 2. To investigate any safety risks that stem from the fact that four type-tests are excluded for verification as a specially tested assembly (STA), as opposed to the seven type tests required for verification as a type-tested assembly (TTA). The document highlights the technical inadequacies of an assembly that is certified as a STA, in accordance with standard SANS 1473-1, and the potential safety risks associated with this type of assembly classification. / Thesis (M.Sc.)-University of KwaZulu-Natal, Durban, 2004.

M. Tech. (Engineering: Electrical, Department Electronic Engineering, Faculty of Engineering and Technology), Vaal University of Technology / The global trends towards energy efficiency have facilitated the need for technological advancements in the design and control of power electronic converters for energy processing. The proposed design is intended to make the practical implementation of converters easier. The development of a universal bidirectional galvanic isolated switch module will be used to drive any MOSFET or IGBT in any position in any topology whether the load is AC or DC. Semiconductor switches are required and are also integrated for fast switching times in power converter applications The structure of the power switch module consists of an opto-coupler which will provide an isolation barrier for maximum galvanic isolation between the control circuitry and power stage. It also consists of a high performance gate drive circuit for high speed switching applications with a floating supply. / Telkom South Africa Ltd, TFMC Pty Ltd, M-TEC, THRIP

Um dos mais importantes elementos que compõem uma rede de telecomunicações é o roteador. Os roteadores modernos empregam sofisticados comutadores para a transmissão de pacotes. A arquitetura de comutadores com filas de entrada exige um processo de escalonamento que estabelece a transferência de pacotes das portas de entrada às portas de saída. O desempenho do sistema depende diretamente do algoritmo de escalonamento, considerando sua vazão e complexidade. Esta dissertação realiza o levantamento teórico dos algoritmos de escalonamento mais relevantes e propõe uma abordagem de escalonamento usando algoritmos genéticos. Um simulador baseado em eventos discretos foi desenvolvido para a realização de testes de desempenho dos escalonadores estudados. O algoritmo proposto, denominado GENIUS, apresentou desempenho relevante e baixa complexidade. / One of the most important components of network telecommunications is the router. Modern routers employ input-queued crossbar switches that require sophisticated scheduling techniques for packet transmission. The architecture of switches with input queues requires an scheduling process that establishes the transfer of packets from input to output ports. The performance of router depends of the scheduling algorithm, considering its throughput and complexity. In this work we survey the most relevant theoretical scheduling algorithms and propose a scheduling approach using genetic algorithms. We developed a simulator of discrete events for testing of schedulers performance. The proposed algorithm, called GENIUS, presents relevant performance and low complexity.

Um dos mais importantes elementos que compõem uma rede de telecomunicações é o roteador. Os roteadores modernos empregam sofisticados comutadores para a transmissão de pacotes. A arquitetura de comutadores com filas de entrada exige um processo de escalonamento que estabelece a transferência de pacotes das portas de entrada às portas de saída. O desempenho do sistema depende diretamente do algoritmo de escalonamento, considerando sua vazão e complexidade. Esta dissertação realiza o levantamento teórico dos algoritmos de escalonamento mais relevantes e propõe uma abordagem de escalonamento usando algoritmos genéticos. Um simulador baseado em eventos discretos foi desenvolvido para a realização de testes de desempenho dos escalonadores estudados. O algoritmo proposto, denominado GENIUS, apresentou desempenho relevante e baixa complexidade. / One of the most important components of network telecommunications is the router. Modern routers employ input-queued crossbar switches that require sophisticated scheduling techniques for packet transmission. The architecture of switches with input queues requires an scheduling process that establishes the transfer of packets from input to output ports. The performance of router depends of the scheduling algorithm, considering its throughput and complexity. In this work we survey the most relevant theoretical scheduling algorithms and propose a scheduling approach using genetic algorithms. We developed a simulator of discrete events for testing of schedulers performance. The proposed algorithm, called GENIUS, presents relevant performance and low complexity.