This thesis addresses the problem of managing computing systems using an integration of model-based control techniques and efficient AI search strategies. The proposed control approach uses the system model to forecast all future system behavior up to a certain horizon and then searches for the best path for the system based on a given utility function. In practical computing systems, however, the large number of control (tuning) options directly affects the computational overhead of the control module which executes in the background at run-time, and ultimately slows down the overall system. To handle this problem, several search algorithms are introduced to improve the controller's performance. This thesis also presents a model integrated framework, referred to as the Automatic Control Modeling Environment (ACME), to facilitate the use of control-based technology for self-management in computation systems. Control-theoretic concepts like above have been investigated and applied successfully to automate the management of computation systems of the control technology. ACME is a domain-specific graphical modeling environment with automated synthesis tools. The framework allows domain engineers to develop models for general computation systems and to capture their performance requirements and operational constraints. The framework can automatically generates executable codes for the controllers based on the given system model and specifications. A case study of an online processor power management is used to demonstrate the effectiveness of the new search techniques for the model-based control approach as well as the application of the ACME.

Multiple cell upsets (MCUs) were first observed in static random access memory (SRAM) in the 1980s. As microelectronics technology scaled, the number of cells affected by an ion strike increased. In order to assess test data, the MCU patterns first need to be associated to mechanisms. This research provides that link by re-evaluating the underlying soft error mechanisms for the SRAM cell and array. Modeling, simulation, and experimental approaches were developed to determine the MCU characteristics and to associate them with mechanisms. The study of SRAM single event upset led to the identification of the well-collapse source-injection (WCSI) mechanism. This mechanism was encountered when charge collection in the well/substrate p-n junction exceeded the amount that can be supplied by the well and/or substrate contacts. When this occurs, the additional photocurrent is supplied by source/body p-n junction diodes in forward-bias. The forward-bias condition injects minority carriers near the MOSFET drains to induce drain current. The WCSI is shown to have a large range of effect, collapsing an entire well and forward-biasing all of the source/body p-n junctions. Technology computer aided design (TCAD) modeling of the WCSI mechanism showed that SRAM cell upset was dependent upon two factors: (1) the forward-bias current and (2) the relative resistances between the source/body p-n junctions and the well-collapse region. These factors enabled the MOSFETs to be replaced with source diodes having an equivalent resistive path. That breakthrough allowed many more devices to be simulated in one TCAD model and enabled the MCU properties of the WCSI mechanism to be understood. A 65-nm SRAM provided experimental data sets containing MCUs; these were analyzed for the WCSI mechanism. The first data set verified TCAD simulations for ion strikes at high incident angles as well as provided many examples of MCU patterns. The second set of data showed that the observed SEU cross section depended upon the SRAM power supply voltage. Overall, the WCSI mechanism increased the number of upsets found in the experimental data.

Surgery requires resection. Some resection is accomplished with a drill. The drill is controlled electronically and with additional circuitry can be controlled by a computer. This thesis describes a means for controlling a surgical drill with a computer such that the drill is disabled except when it is a predefined safe zone. Software provides a human-machine interface for displaying CT images of anatomy to be resected and for displaying the current position of the drill tip. The interface allows the operation to (a) register physical space to CT space, (b) track the drill, and (c) control the drill automatically. The software is written in C++ with the help of open-source libraries to run under the Microsoft Windows operating system. Results of tests of the accuracy of the system are provided.

Triple-well NMOSFETs collect more charge as compared to dual-well NMOSFETs. Single event charge collection mechanisms in 90 nm triple-well NMOS devices are explained and compared with those of dual-well devices. The primary factors affecting the single event pulse width in triple-well NMOSFETs are the separation of deposited charge due to the n-well, potential rise in the p-well followed by the injection of electrons into the p-well by the source, and removal of holes by the p-well contact. Design parameters of p-wells, such as contact area, doping depth and placement, are varied to reduce single event pulse widths. Pulse width decreases as the area of the p-well contacts increases, the p-well contacts becomes deeper, and the p-well contacts are placed more frequently. Increasing the p-well n-well junction depth also causes the full width half rail (FWHR) pulse width to decrease. In long p-wells with multiple transistors present in them, a potential gradient occurs along the body of the well as regions of the well away from the strike remain unaffected.

Energy depositions from highly ionized particles in space environments can induce transient current (voltage) pulses in microelectronic devices, called Single Event Effects (SEEs). This thesis uses simulations to investigate the single event response of a low power operational amplifier (Op Amp) designed in IBM 5AM (0.5 um) SiGe BiCMOS technology. Cadence Spectre, using single event current pulses similar to those produced using 3D TCAD simulations, were applied to simulate the Op Amp response for multiple circuit configurations. Key findings include long (>> 1ms) output perturbations for strikes to input bias devices, which induce currents well beyond the bias current used for the low power design. Unity gain configuration exhibited the longest perturbation among the simulated variants. Variation of single event pulse parameters exhibit relative insensitivity to temporal profiles for a given deposited charge, indicating that integrated charge drives the response given the relative fast (~ nanosecond) scale of the event compared to the slower output response time. Simulation results are used to estimate the effectiveness of radiation hardened by design (RHBD) variants of the heterojunction bipolar (HBT) devices used in the input stage in reducing the sensitive cross section. Results indicate that the guard rings may reduce the cross section for moderate to high LET values.

With shrinking device feature sizes, integrated circuits are becoming more vulnerable to Single-Event Transients (SETs). Characterizing error rates due to SETs is essential for choosing appropriate hardening techniques to assure a digital circuits radiation tolerance. However, single-event testing may be expensive, complicated and time consuming. This thesis has illustrated how built-in self-testing alternatives can be used to estimate the radiation response of a circuit without costly equipment and test facilities. The BIST, by electrically injecting pulses of randomly varying width and arrival times with respect to the clock, mimic the actual SET unpredictability. Simulation and experimental results from the 180 nm technology node show that pulses in the range of 300 ps to about 5 ns can be generated. With the use of equivalent-inputs, the number of nodes for BIST testing may be reduced by orders of magnitude below the actual node count of the circuit. In the case of the 16-bit adder and 4-bit multiplier, about 80% of the total soft errors can be accounted for by testing only 5% of the nodes in the circuit. These results demonstrate the feasibility of the BIST technique for testing complex ICs intended for radiation environments in a very cost-effective manner. The area penalty for implementing a BIST circuit will vary according to the application, but will be minimal for larger circuits. In a nutshell, BIST is a cost effective method of testing for SETs in any conventional laboratory that can give an overall estimate of the circuits vulnerability to single-events.

CVD diamond is an excellent material for field emission with low electron affinity, robust mechanical and chemical properties, high thermal conductivity, and ability to withstand extreme temperature and radiation. However, utilization of the properties of diamond in vacuum micro/nanoelectronics and other fields has been limited by the complexity associated with its process integration. Nanocrystalline diamond is an emerging form of the material, vastly expanding its utility for applications ranging from electronics to tribology. Its distinct properties, including small grain size, controlled amounts of sp^2-carbon, high electrical conductivity from n-type dopant (nitrogen) incorporation, and a smooth, uniform surface morphology, offer wide latitude for materials processing and integration for device formation. This research is focused on the design, fabrication, and characterization of nanodiamond vacuum microelectronic devices, specifically on monolithic lateral field emission diodes, triodes, and transistors, developed using a consistent process scheme, paralleling semiconductor IC fabrication technology. Reliable process techniques have been developed to grow and micropattern nitrogen-incorporated nanodiamond thin films, with grain size as small as 5 nm, and integrated in the fabrication of lateral field emitter array (FEA) devices. A lithographically controlled finger-like emitter geometry and small interelectrode spacing in a low-capacitance integrated structure, achieved by single-mask processing are attributes of the lateral devices. The nanodiamond lateral emitters demonstrate promising characteristics of low turn-on voltage (~ 5 V) and threshold electric field (1.1 V/ìm), high emission current (25 mA) and current density (183 µA/finger), with reliable and stable performance. These electron devices exhibit high diode rectification (> 10^4), and a large transconductance (0.3 µS/finger) as a gated microtriode. The monolithic vacuum transistor, in planar lateral configuration, shows negligible gate intercepted current (Ig/Ia ratio ~ 0.001 %), current saturation, and large amplification factor of ~ 200. Moreover, this research has led to the development of the first vacuum microelectronic technology with operational temperature immunity (> 350 C) and radiation hardness (tested upto 20 MRad total dose and 4.4x10^13 neutrons/cm^2 exposure). These diamond vacuum device characteristics signify a novel, efficient means of accomplishing IC-compatible electronics, suited for high-speed, high-frequency and high-power, extreme-environment applications.

Application of advanced technology in remote, extreme environments can reduce system power, reduce launch weight and improve the overall reliability of the space mission. The Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) has been shown to have high tolerances to total ionizing dose. Furthermore, SiGe BiCMOS, a process technology implementing both SiGe HBT and Complimentary Metal Oxide Semiconductors (CMOS), has been shown to have the necessary performance to operate at cold temperatures. These features of this technology are essential in order to work in the above extreme environments. However, further study is needed to understand how BiCMOS reacts to Single Event Effects (SEE). The focus of this research is to study the CMOS portion of the BiCMOS process implemented as a Static Random Access Memory (SRAM) cell. By simulating an SRAM cell with Technology Computer Aided Design (TCAD) using a newly developed mixed-mode capability, this research shows that the digital CMOS SRAM cell has an increased sensitivity to Single Event Upsets (SEUs) at reduced temperatures driven by increased charge collection due to an increase in carrier mobilities. However, this increased sensitivity is still below the thresholds required to cause problems for the error management system for the memory cell and therefore radiation hardening will not be required for the SRAM at the cell level.

Carbon Nanotube (CNT) is an emerging form of carbon nanostructure, vastly expanding its utility for several applications ranging from electronics to tribology. CNT is an excellent material for electron field emission due to its high aspect ratio, robust mechanical and chemical properties, high thermal conductivity, and ability to withstand high temperature and ion bombardment. This research is focused on the fabrication and characterization of a novel CNT field emission cell with a built-in electron beam source for electron excited amplified field emission. In brief, reliable and consistent process techniques have been developed to grow aligned CNTs under different growing conditions using MPCVD. This process was integrated in the fabrication of monolithic lateral field emission cell (FEC) in diode configuration with a built-in electron beam source. Field emission behaviors with and without activation of the built-in electron beam were characterized. A high voltage of 1.8 kV was applied to generate the bombarding electron beam on the FEC. The emission current of the FEC increases markedly with the activation of the electron beam source due to impact ionization and direct interaction with the FEC CNT cathode. The emission behaviors were confirmed by F-N plots. It was found that ~ 10 times current amplification was achieved. These results demonstrate the feasibility of a novel means of power generation using electron stimulated impact ionization field emission.

The constant race for increasing the chip density in semiconductor integrated circuits has not only decreased the minimum device feature size but also the minimum amount of charge required to represent a HIGH node voltage. In the radiation domain, this translates into reduced charge requirements for generating a Single-Event Transient (SET) and the resulting Single-Event Upset (SEU). Most of the hardening techniques to combat these effects have focused on the propagation of SET pulses through logic gates, without regard to interconnects between them. In these nanoscale technologies, scaling and closely packed interconnects magnify crosstalk effects causing a SET pulse to affect multiple logic paths instead of the single hit path. Such events increase the vulnerable area and the SET susceptibility of complementary metal-oxide-semiconductor (CMOS) circuits. This research analyses factors affecting the crosstalk pulse due to a SE in digital logic circuits for sub-100 nm technologies. Specifically, the threefold objective of this research has been achieved: (i) the factors that exacerbate SE induced coupling identified using simulations and modeling (ii) a sample circuit designed, fabricated and tested to provide the first ever experimental measurement of SE induced interconnect crosstalk; and (iii) design margins and mitigation techniques to contain this effect provided. Simulation and Laser absorption experimental results obtained substantiate that the effects of Single Event (SE) induced crosstalk depend greatly on (i) the dV/dt of the aggressor pulse voltage, (ii) the interconnect length (coupling capacitance) and (iii) the driving strengths of devices connected to the aggressor and victim lines. This work has presented to the radiation effects community a new phenomenon that is gaining significance with scaling technologies and the use of commercial foundries to fabricate parts for space. As the semiconductor industry keeps up with the scaling trend of increased chip density and interconnect routing complexity, SE induced crosstalk effects are inevitable. Judicious design and layout planning using analyses performed in this dissertation can help mitigate or contain this effect.