Chronic Deep Brain Stimulation (DBS) has been a rapidly evolving area of neurotherapeutics since its initial introduction for the treatment of Parkinsons disease and essential tremor in the 1990s. In the recent past, there has been active research to improve the outcome of the procedure as well as to make it more accessible to patients. This dissertation is broadly categorized into two parts. The first is motivated by a lack of standardization in the localization of popular anatomical landmarks used to indirectly localize as well as communicate stereotactic targets. Inter-surgeon variability in manually selecting these landmarks and its impact on target localization is shown to be substantial. A method based on non-rigid image registration is used for automatic prediction of the landmarks and its accuracy is shown to be sub-millimetric in both clinical and non-clinical settings. The second part is motivated by shortcomings and inaccuracies in existing methods to populate statistical atlases of electrophysiological data acquired intra-operatively during DBS surgeries. A Gaussian smoothed spherical shell kernel is proposed as an improvement over an existing method to model stimulation response in order to build accurate statistical maps. The effect of intra-operative brain shift on the creation of electrophysiological atlases is investigated and shown to be substantial. An approach to build low-shift atlases is proposed and statistical maps of stimulation response built using data from such an atlas are shown to correlate strongly with a statistical ground truth as well as with an anatomical atlas. Finally, in a preliminary study, it is shown that statistical maps of adverse effects combined with statistical maps of efficacious stimulation response could be clinically useful for post-operative programming assistance in DBS.

Ambient hydrogen has been shown to enhance the degradation of several types of linear bipolar devices. Recently, it has been seen that hydrogen exposure can cause increased degradation at high dose rates. This has created interest in investigating the possibility of an accelerated hardness assurance test involving irradiation at high dose rates during a hydrogen soak. This thesis investigates the various factors that determine the effects of hydrogen on bipolar and MOS devices and discusses the risks involved in using hydrogen screening as an accelerated hardness assurance test. Hydrogen soaking experiments are performed to evaluate the dependence of defect buildup and annealing in gated lateral bipolar transistors on hydrogen exposure. Comparisons of the radiation responses of transistors tested in 2009 to identical devices from the same wafer tested in 2003 show that aging has reduced the amount of radiation-induced interface trap and oxide trapped charge formation in most cases. These results demonstrate that hydrogen has a dual role and that the way in which the radiation response of a hydrogen-sensitive device evolves with age depends on whether hydrogen is diffusing into or out of the device, and whether the initial defect concentration favors passivation or depassivation reactions. These results strongly suggest that hydrogen exposure cannot replace low-dose-rate irradiation in ELDRS tests for bipolar devices and ICs without extensive characterization testing.

A reliability concern of growing interest in the microelectronics community is the deleterious effect of ionizing radiation. The so-called "single events" single particles which can penetrate semiconductor material leaving ionized charge in their wake can cause information corruption and transient system failure. Single events (SE) are ubiquitous this radiation emanates from processing and packaging material integral to a circuit, as well as the environment external to a circuit. Once only the concern of space-bound systems, integrated circuit (IC) density and power scaling have propelled this issue to the forefront of reliability concerns at current technology nodes. In mixed-signal systems, the effect of an SE particle strike is the generation of a transient signal (single-event transient or SET) that competes with the legitimate signals propagating through a circuit or perturbs the functionality of the circuit. There is a particular interest in the effect of SETs on the phase-locked loop (PLL) because of the propensity to cause loss of frequency integrity, and the resultant wide-spread impact on high-performance systems. This dissertation applies both circuit-level simulations and experimental testing to characterize SETs in a common PLL topology. The simulations and experimental procedures target the PLL sub-circuits so that individual contributions to the overall PLL SET vulnerability are distinguished and analyzed. Additionally, novel analyses are offered that effectively predict the relative contributions of SET generation within the PLL. Furthermore, the analyses are utilized to develop a generalized model for single transient propagation through the PLL. Although this work primarily discusses PLLs in the context of on-chip clock generation and skew reduction in the presence of ionizing particles, it is the goal of this work to present a broad-spectrum model for single transient propagation through PLL topologies for a variety of applications and operating environments. The transient model is formulated from a conventional linear PLL model commonly used in a variety of noise analyses. However, the model is unique in that the resulting fundamental design equations are derived in closed-form under the assumption that transients are a result of single impulses applied to the various sub-circuits rather than continuous nondeterministic sources. This approach vastly simplifies the analysis and provides insight into the closed-loop parameters that directly influence the generation and propagation of transients through the PLL. Moreover, a novel design parameter, the PLL critical time constant, is discovered to be the fundamental factor determining the ease at which transients influence the output phase displacement. As a result, a comprehensive set of design guidelines for analytical transient mitigation is developed and applicable to all PLL topologies subject to single transient phenomena.

Advances in fabrication technologies for semiconductor integrated circuits (ICs) have resulted in sub-100 nm feature sizes. Along with this desired reduction in dimension has come an undesired increase in vulnerability of flip-flops to soft errors, which are caused by energetic particles that either directly or indirectly deposit energy, and create electron-hole pairs in the semiconductor material. These charges, when collected at a circuit node, perturb the associated node voltage, creating a transient pulse, which may alter the data stored in the flip-flop, causing a single- event upset (SEU). Decreasing technology feature size has resulted in higher packing densities, as a result of which, single-event related charge might be collected at multiple nodes in a circuit. Circuit-level simulations predict increased vulnerability of flip-flop designs and increased occurrence of single-event upsets in advanced technologies due to multi-node charge collection from single-ion strikes. This trend is examined by simulating 3D models of the flip-flops in a terrestrial neutron environment using Monte-Carlo Radiative Energy Deposition (MRED) simulations for charge deposition in several technology generations.

The majority of modeling and simulation of single event transients (SETs) and their effects is normally done at a transistor level, known as micro-modeling. These simulations give insight into how a transistor will behave when struck by SETs. The micro-modeling of single-particle effects in Integrated Circuit (IC) devices can simulate charge collection, charge deposition/generation and ionic interaction with the semiconductor material. Micro-modeling works very well on a small circuit, when there are a low number of transistors. However, modeling large circuits on a transistor level can be time- and cost-consuming. System-level modeling and simulation allow for large circuits to be simulated in less time and less cost. Under the correct conditions, the results of macro-modeling (system-level) can approximate the results of micro-modeling. This thesis focuses on the simulation of SETs that last longer than one clock cycle from a macro-modeling perspective. Simulating the SETs is done through the transient fault injection method. Transient fault injection is the method of injecting a fault on a certain node and observing what happens as it propagates through the circuit. It discusses the design and simulation of both a 4x4 serial full adder implemented multiplier and a 4x4 parallel full adder implemented multiplier. The burst error mitigation approaches used in communication theory are discussed and compared with the results of the multipliers. The results are compared for SETs of clock cycle lengths 1, 6 and 36 that are applied to all the nodes for a 16x16 serial full adder implemented multiplier and a 16x16 parallel full adder implemented multiplier. A frequency analysis is presented for the both multipliers with no SETs, a SET of length 6 and a SET of length 36.

Indium Arsenide (InAs) channel High Electron Mobility Transistors (HEMTs) with Aluminium Antimonide (AlSb) barriers are an exciting option for low power RF applications due to excellent quantum well confinement and very high low-field electron mobility. The fundamental degradation trends and mechanisms for the device are yet to be adequately understood. In this thesis, a detailed analysis of DC and RF degradation under hot carrier stress is presented. Based on electrical stress performed on devices with varied starting characteristics, we show that some devices are severely degradation prone in operating conditions where the electric field in the Indium Arsenide channel and the impact ionization rate are simultaneously high. Annealing results, coupled with device simulations and Density Functional Theory (DFT) calculations, show trends consistent with an oxygen-induced metastable defect in AlSb dominating the device degradation. Some physically abundant impurities like Carbon and Tellurium are shown to be unlikely candidates for producing the observed degradation. When stressed with hot carriers or under high impact ionization conditions, the majority of the devices show negligible change in DC characteristics, but appreciable degradation in peak fT. Short access region lengths exacerbate the degradation, which can be traced to a reduction in peak RF gm, resulting either from reduced hole mobility or a stress-induced increase in thermodynamic relaxation time of electrons in the channel. Increase in parasitic capacitances after stress is shown to have a secondary contribution to the degradation in devices with long access regions. For devices with short access regions a post-stress increase in gate to source parasitic capacitance (Cgs) significantly adds to degradation caused by reduction in peak RF gm.

Effective communication and user input are crucial to mobile human-robot interaction tasks, especially in cases where robots are deployed to assist with disaster relief, emergency response, or military applications. This thesis details the design and implementation of a mobile, map-based tasking interface that leverages novel communicative and interactive methods to facilitate the completion of mobile Human-Robot Interaction tasks. In particular this interface employs Multi-Touch capabilities on an intermediate sized device, such as a tablet computer, to permit individuals to task and supervise robots. The primary objective is to develop an interface that will allow a mobile supervisor to oversee a team of robots while interacting with other humans. This thesis focuses on the development and evaluation of two fundamental components necessary to achieve the primary objective. A Communications Mode was developed to facilitate the rapid and effective communication of relevant information between individuals. A user evaluation was conducted to determine the usability of the Communications Mode compared to a paper-based and an audio-based communication method. Findings from this user evaluation determined that the Communications Mode was superior to the audio-based method and was at least as good as the paper-based method. This thesis also explores the fundamental differences between mouse-based and touch-based interaction when performing drawing tasks by comparing error rates and drawing speed using each of the two interaction methods. A user evaluation determined that, for drawing tasks, users commit more errors using touch-based interaction, but also complete tasks faster than when using mouse-based interaction due to a higher average drawing speed. Finally, this thesis proposes and evaluates four methods for the reduction of user input, either via mouse or Multi-Touch, during drawing tasks. Data reduction is essential because users frequently supply unnecessary information, in the form of excess points on the screen, while performing a drawing task. Reduction methods were compared by the resulting error generated compared to a users true input and the amount of reduction each method afforded. A user study determined that, of the four methods, Cubic Iterative reduction yielded the best reduction with an acceptable rate of error.

Passive devices are micro circuit elements that play a critical role in electronic products. The extraordinary physical properties of diamond such as high thermal conductivity, small thermal coefficient of expansion and hardness present intriguing possibilities for the fabrication of microstructures which benefit from an extended dynamic range, faster response, or reduced degradation. We have successfully fabricated miniature powered freestanding diamond resistors that demonstrated an ability to "glow" under power pulse loading and handle very high power density. These resistors are isolated from the substrate by a cavity. The freestanding diamond resistors were heated with voltage pulses such that the diamond resistors experienced thermal emission from Joule heating. They were examined for their electrothermal behavior including measurements of their infrared emission under power pulse loading and their dynamic thermal response. The freestanding resistors were found to withstand higher power than equivalent attached diamond resistors and could operate at power density levels well over 3x that of conventional passive power resistors.

Analog-to-digital converters (ADCs) are necessary circuits in many space, military, and medical circuit applications. Intelligence, surveillance, reconnaissance, and communication missions all require high performance ADCs. Speed, resolution, and power are concerns in high performance designs. Unlike commercial applications, space, military, and some medical electronics must also be able to function in a radiation environment. This additional complexity provides an interesting and needed area of research. <p> The goal of this work is to understand single event effects (SEEs) in high-speed ADCs, so the impact of design topologies and mitigation techniques can be evaluated for Department of Defense (DOD) or commercial space deployment. This goal is broken into two parts. The first part characterizes and explains the single event effect response, and presents a novel method of evaluating SEEs in ADCs through the use of frequency domain analysis. The second part provides additional circuit design alternatives for hardening pipelined ADCs: the use of comparator triple modular redundancy or robust encoder logic in the front pipeline stages, dual-path hardening in switched-capacitor sub-circuits, and applying analog layout techniques to all transistors-pairs along the fully-differential signal path. The conclusion of this work helps designers achieve ADCs for the next generation applications, influence experimental testing methodologies, and applies to other high-speed mixed signal applications.

Radiation effects on Ge pMOS devices have been presented in this thesis. The irradiation and annealing responses of Ge pMOSFETs are investigated as a function of device processing. Transmission gate bias is found to be the worst-case irradiation bias condition. Junction leakage increases with total dose, which leads to a decrease in the ION/IOFF ratio. The ION/IOFF ratio recovers with room temperature annealing. Both band-to-band tunneling and trap-assisted tunneling contribute to the observed leakage. Device leakage before and after irradiation is found to be sensitive to halo implant dose and the number of Si monolayers at the Ge/insulator interface. Interface trap densities and body leakage also increase with dose and decrease with annealing. Both the radiation-induced charge trapping and the low frequency (1/f) noise increase with total ionizing dose and decrease with annealing time. The smallest increases in noise after irradiation are observed for Ge pMOSFETs with the lowest halo implantation doses. The smallest increases in oxide and interface trap charge densities are obtained for devices with eight monolayers of Si at the interface, as compared to devices with five Si monolayers.