HMS Industrial Networks AB is in need of changing a communications solution that iscurrently based on an ASIC. This will be achieved by moving the communications solution toa FPGA with the help of the programming language VHDL. By doing this, it is possible toreduce the need for specific circuits, get a more flexible platform and thus get a cheapersolution. This report describes a solution for how to move a network protocol from an ASIC to anFPGA. The report shows that the network slave device is working under the guidelines forthis project. This means that it is quite realistic to implement a fieldbus protocol on an FPGA,using VHDL and to maintain the same functionality as the earlier communications solution.

Summary  Today we are probably on a point of change for the car industry. The last century was the century of vehicles with internal combustion engines. Fossil fuels were relative cheap, easy accessible and they have a high specific energy. The pollution and dependency on oil caused the last decade an increasing demand for alternatives. Alternatives for electric power plants and for car drives. Yet the turnover to hybrids is a fact and much research is done for pure electric vehicles. Research about the control of electric motors is by that become a hot topic. To simulate an electric vehicle drive with an induction motor, a frequency converter is needed. This combination of motor and converter led to many possible experiments. With a few experiments already done and a broad theoretical background report this thesis provides a good bundle of information to start with further experiments. The experiments can become even broader when a flywheel is added as mass inertia momentum and a DC source on the DC-link. Both elements contribute for a better simulation of an electric motor in an electric vehicle. What is described in this theoretical report about the combination of an induction motor and converter is only the tip of the iceberg. I had too less time to begin experimenting with the flying wheel. The DC-link voltage becomes ca. 540V. From the perspective of safety I could never work alone with the DC-link. Even with a companion it was too dangerous because the equipment of the Halmstad University is not made for such dangerous voltages. That’s why this thesis contains more theoretical background and less actual practical data. / SAMENVATTING Momenteel bevinden we ons in een tijd van omslag. Na een eeuw waarin de brandstofmotor het transportlandschap domineerde, is er nood aan een alternatief. Fossiele brandstof zorgt voor schadelijke uitlaatgassen bij verbranding en de afhankelijkheid van andere landen voor de bevoorrading van fossiele brandstof blijft altijd een risicofactor. De eerste stap in deze verandering is gezet met de ontwikkeling van hybride wagens. De toekomst zal waarschijnlijk helemaal elektrisch worden. Daarom is het onderzoek naar de controle van elektrische motoren belangrijk. In de universiteit van Halmstad zijn er verscheidene inductiemotoren aanwezig in het elektriciteitslabo. De doelstelling was dat ik een frequentieomvormer selecteerde, bestelde en parametreerde op basis van deze motoren. Daarnaast kreeg ik de vrijheid om een elektrische wagen te simuleren. Dit zou ik doen door een vliegwiel voor de traagheid en door een batterij na te bootsen om de DC-link te voeden. Al mijn informatie moest ik bundelen in deze thesistekst zodat het eventueel een handige bundel werd voor toekomstige studenten die willen werken met de convertor. Ik had slechts 2 maanden de tijd om dit uit te voeren, metingen te doen en een theoretisch verslag te schrijven. Vanwege deze korte tijdspanne was het niet mogelijk het vliegwiel te implementeren. Daarnaast was de tussenkringspanning ongeveer 540V DC. Dit is zeer gevaarlijk zodat ze liever hadden dat ik de proeven met een gesimuleerde batterij liet varen. Dit verklaart enigszins waarom uitgebreide meetresultaten ontbreken en deze thesis vooral een bredere theoretische toets heeft.

This report describes a thesis done at the Jönköping University of Technology. The aim of this thesis was to create conditions to optimize an existing automatic electrostatic coating system by changing the technology for dispensing lacquer. To select the technology, a study of different dispensing techniques carried out which concluded that the piezoelectric membrane and electrostatic atomization are the most interesting techniques. In order to perform tests with dispensing techniques a demonstrator has been optimized. The controller and PC software of the demonstrator has been programmed to be able to send out PWM signals that control the dispensers. An adapter card was designed to control the piezoelectric membrane and a steering link to the electrostatic atomization has been developed for PWM signals up to 500V. The work has laid ground for a demonstrator where further testing of the dispensing technologies can be performed. / Den här rapporten beskriver ett examensarbete utfört vid Jönköpings tekniska högskola. Målet med arbetet var att skapa förutsättningar för att optimera ett befintligt automatiskt elektrostatlackeringssystem genom att byta ut tekniken för dispensering av lack. För att välja teknik har en undersökning av olika dispenseringstekniker genomförts där man kommit fram till att piezoelektriska membran och elektrostatisk atomisering är de tekniker som är mest intressanta. För att kunna utföra tester med dispenseringsteknikerna har en befintlig testutrustning (demonstrator) anpassats för ändamålet. Demonstratorns kontrollerkort och PC-program har programmerats om och anpassats för att kunna sända ut PWM-signaler som styr dispenseringen. Ett adapterkort har konstruerats för att kunna styra piezoelektriska membran och en styrkoppling till elektrostatisk atomisering har tagits fram för PWM-signaler upp till 500V. Arbetet har lagt grunden till en demonstrator där vidare tester av dispenseringsteknikerna piezoelektriska membran och elektrostatisk atomisering kan utföras.

Detta examensarbete behandlar problemet med att testa inbyggda system i kontorsmiljö. För att göra detta och därigenom kunna göra anrop på det inbyggda systemets API, måste detta anrop skickas som ett seriellt datapaket över en seriell kommunikationslänk som TCP/IP. Detta möjliggjordes genom att först upprätta en kommunikationslänk med protokollet TCP/IP, där användningen av POSIX-sockets tillämpades. För att packa ner och packa upp funktionsanropen till seriell data implementerades ett protokoll som följdes när detta utfördes. Hantering av data i samband med överföring över TCP/IP sköttes av ett protokoll vid namn BGSFP, ett protokoll som bygger på det tidigare protokollet TSFP.

The main goal in this thesis is to select and test Forward Error Correction (FEC) schemes suitable for network video transmission over RTP/UDP. There is a general concern in communication networks which is to achieve a tradeoff between reliable transmission and the delay that it takes. Our purpose is to look for techniques that improve the reliability while the realtime delay constraints are fulfilled. In order to achieve it, the FEC techniques focus on recovering the packet losses that come up along any transmission. The FEC schemes that we have selected are Parity Check algorithm, ReedSolomon (RS) codes and a Convolutional code. Simulations are performed to test the different schemes. The results obtained show that the RS codes are the more powerful schemes in terms of recovery capabilities. However they can not be deployed for every configuration since they go beyond the delay threshold. On the other hand, despite of the Parity Check codes being the less efficient in terms of error recovery, they show a reasonable low delay. Therefore, depending on the packet loss probability that we are working with, we may chose one or other of the different schemes. To summarize, this thesis includes a theoretical background, a thorough analysis of the FEC schemes chosen, simulation results, conclusions and proposed future work.

An analog-to-digital converter (ADC) is a link between the analog and digital domains and plays a vital role in modern mixed signal processing systems. There are several architectures, for example flash ADCs, pipeline ADCs, sigma delta ADCs,successive approximation (SAR) ADCs and time interleaved ADCs. Among the various architectures, the pipeline ADC offers a favorable trade-off between speed,power consumption, resolution, and design effort. The commonly used applications of pipeline ADCs include high quality video systems, radio base stations,Ethernet, cable modems and high performance digital communication systems.Unfortunately, static errors like comparators offset errors, capacitors mismatch errors and gain errors degrade the performance of the pipeline ADC. Hence, there is need for accuracy enhancement techniques. The conventional way to overcome these mentioned errors is to calibrate the pipeline ADC after fabrication, the so-called post fabrication calibration techniques. But environmental changes like temperature and device aging necessitates the recalibration after regular intervals of time, resulting in a loss of time and money. A lot of effort can be saved if the digital outputs of the pipeline ADC can be used for the estimation and correctionof these errors, further classified as foreground and background techniques. In this thesis work, an algorithm is proposed that can estimate 10% inter stage gain errors in pipeline ADC without any need for a special calibration signal. The efficiency of the proposed algorithm is investigated on an 8-bit pipeline ADC architecture.The first seven stages are implemented using the 1.5-bit/stage architecture whilethe last stage is a one-bit flash ADC. The ADC and error correction algorithms simulated in Matlab and the signal to noise and distortion ratio (SNDR) is calculated to evaluate its efficiency.

Detta är en rapport för ett 15hp examensarbete på Linköpings Tekniska Högskola. Projektet syftar till att implementera ett digitalt frekvensutjämningsfilter för audioapplikationer i ett Atmel DE2 FPGA utvecklingskort. Specifikt ska systemet användas till att korrigera ojämnheter i in-ear hörlurars frekvenssvar. Denna rapport är en beskrivning av systemets utformning och hur arbetet gick till väga. Resultatet blev ett väl fungerande system och ett antal förslag på förbättringar. / This is a report for a 15hp thesis at the Institute of Technology at Linköping University. The project aims to implement a digital frequency-equalizing filter for audio applications in an Atmel DE2 FPGA development board. More specifically the system will be used to correct unevennesses in the frequency response of in-ear earphones. This report is a description of the design of the system and how the work on the project was executed. The result was a well functioning system with suggestions on possible improvements.

The recent increase of mobile data usage and emergence of new applications such as Online Gaming, mobile TV, Web 2.0, Streaming Contents have greatly motivated the 3rd Generation Partnership Project (3GPP) to work on the Long Term Evolution (LTE). The LTE is the latest standard in the mobile network technology tree. It inherits and develops the GSM/EDGE and UMTS/HSPA network technologies and is a step toward the 4th generation (4G) of radio technologies designed to optimize the capacity and speed of 3G mobile communication networks. In this thesis, the LTE system capacity and coverage are investigated and a model is proposed on the base of the Release 8 of 3GPP LTE standards. After that, the frequency planning of LTE is also studied. The results cover the interference limited coverage calculation, the traffic capacity calculation and radio frequency assignment. The implementation is achieved on the WRAP software platform for the LTE Radio Planning.

The Analog to Digital Converter (ADC) is an inevitable part of video AnalogFront Ends (AFE) found in the electronic displays today. The need to integratemore functionality on a single chip (there by shrinking area), poses great designchallenges in terms of achieving low power and desired accuracy.The thesis initially focuses upon selection of suitable Analog to Digital Converter(ADC) architecture for a high definition video analog front end. SuccessiveApproximation Register (SAR) ADC is the selected architecture as it scales downwith technology, has very less analog part and has minimal power consumption.In second phase a mathematical model of a Time-Interleaved Successive ApproximationRegister (TI-SAR) ADC is developed which emulates the behavior ofSAR ADC in Matlab and the errors that are characteristic of the time interleavedstructure are modeled.In the third phase a behavioral model of TI-SAR ADC having 16 channels and12 bit resolution, is built using the top-down methodology in Cadence simulationtool. All the modules were modeled at behavioral level in Verilog-A. The functionalityof the model is verified by simulation using signal of 30 MHz and clockfrequency of 300 MHz, using a supply voltage of 1.2 V. The desired SNDR (Signalto Noise Distortion ratio) 74 dB is achieved.In the final phase two architectures of comparators are implemented in 65nmtechnology at schematic level. Simulation results show that SNDR of 71 dB isachievable with a minimal power consumption of 169.6 μWper comparator runningat 300 MHz.NyckelordKeywords

Today, more and more embedded hardware devices are reaching the market and consumers with a demand for smaller and better devices than yesterday. Increasing the performance of a device decreases the operating time since more power is consumed, still, decreasing the size of the device also decreases operating time as the battery size decreases.To allow the performance to increase and the size of the device to decrease, the designer must nd techniques allowing the hardware to consume less power during normal usage of a device than during the peak usage.In this thesis an implementation of an ARM based microprocessor system is presented and used for measuring and evaluation of the power consumption possibilities of the system.