To properly display digital X-ray images for visual diagnosis, a proper display range needs to be identified. This can be difficult when the image contains collimators or large background areas which can dominate the histograms. Also, when there are both underexposed and overexposed areas in the image it is difficult to display these properly at the same time. The purpose of this thesis is to find a way to solve these problems. A few different approaches are evaluated to find their strengths and weaknesses. Based on Local Histogram Equalization, a new method is developed to put various constraints on the mapping. These include alternative ways to perform the histogram calculations and how to define the local histograms. The new method also includes collimator detection and background suppression to keep irrelevant parts of the image out of the calculations. Results show that the new method enables proper display of both underexposed and overexposed areas in the image simultaneously while maintaining the natural look of the image. More testing is required to find appropriate parameters for various image types.

The ad hoc Offshore Accords signed between the Martin Government, and each Newfoundland and Nova Scotia have fundamentally altered the landscape of regional redistribution in Canada. The fallout from the Accords has had an immediate impact on the functioning of the Equalization Program and the political factors that inform debate over future reforms. This thesis examines the factors that led to the February 2005 Offshore Accords. It also examines the case of Saskatchewan's treatment under the Equalization Program

A combined solution of the Feed-Forward Equalizer (FFE) and Near-End Crosstalk (NEXT) noise cancellation technique was suggested. The techniques increase data throughput and improve link quality in the 20-in FR4 legacy backplane application. Backplane channel loss and coupling noise were measured and characterized to develop the corresponding behavioral channel model. The receiver-side FFE with 4-tap Finite Impulse Response (FIR) filter structure was adopted as the optimum equalizer topology. The 4-tap FIR filter consists of tap delay line with tap-spacing 33 ps and linear tap-gain amplifiers. The tap coefficients were calculated with the Minimum-Mean-Squared-Error (MMSE) algorithm. A 0.18-um CMOS 4-tap FIR filter IC was designed and fabricated. The experiment results showed the 20-Gbit/sec 4-PAM and 10-Gbit/sec NRZ signal were successfully equalized for the 20-in FR4 legacy backplane channel. Moreover, the suggested NEXT noise cancellation technique consists of coarse- and fine-cancellation stages. The 0.18-um CMOS building block ICs such as 7-tap FIR filter, tunable active Pole-Zero (PZ) filter, and a temporal alignment delay line were fabricated. The experiment results showed that 6-dB Signal-to-Noise Ratio (SNR) improvement was achieved by the developed NEXT noise cancellation technique.

The objective of the proposed research is to realize a 10-Gb/sec serial data link over band-limited channels, such as backplanes, multi-mode fiber, and copper-based cables that were originally designed for data rates less than 1Gb/sec. This is achieved using electrical equalization implemented in an integrated circuit (IC). To successfully compensate for various band-limited channels at the targeted data rate with a single equalizer IC, a reconfigurable equalizer topology is proposed. In order to realize the proposed goal, various channels are characterized of their forward transmission frequency response. Based on the measured channel data, system simulations are performed to identify the required specifications for IC implementation. This provides information such as optimal number of taps, fractionally-spaced tap delay, and tap coefficients for the proposed IC. With the obtained system requirements, IC building blocks are designed and fabricated in a 0.18- and #956;m CMOS technology. The fully-integrated reconfigurable CMOS equalizer provides a single-chip solution for compensating various band-limited channels. This enables 10-Gb/sec serial data transmission achieving signal integrity beyond their designed specifications.

This dissertation develops an unclocked receiver analog decision-feedback equalizer (ADFE) circuit architecture and topology and implements the circuit in 0.18-um CMOS to enable 10-Gb/sec serial baseband data transmission over FR-4 backplane and optical fibre. The ADFE overcomes the first feedback-loop latency challenge of traditional digital and mixed-signal DFEs by separating data re-timing from equalization and also eliminates the need for clock-recovery prior to decision-feedback equalization. The ADFE enables 10-Gb/sec decision-feedback equalization using a 0.18-um CMOS process, the first to do so to the author s knowledge. A tuneable current-mode-logic (CML) feedback-loop is designed to enable first post-cursor cancellation for a range of data-rates and to have external control over loop latency over variations in process, voltage and temperature. CML design techniques are used to minimize current consumption and achieve the required voltage swing for decision-feedback to take place. The all-analog equalizer consumes less power and area than comparable state-of-the art DFEs. The ADFE is used to compensate inter-symbol interference (ISI) for 20 inches of FR-4 backplane and 300 m of multi-mode fibre at 10-Gb/sec. The ADFE also extends the reach of single-mode fibre at 10-Gb/sec to 120 km. The work described in this dissertation advances the state-of-the-art in equalization solutions for multi-Gb/sec serial data transmission and can find applications in several of the 10-Gb/sec Ethernet standards that have been approved recently. The contributions of this work toward future research are also discussed.

Channel order estimation is an important problem in many fields including signal processing, communications, acoustics, and more. In this thesis, blind channel order estimation problem is considered for single-input, multi-output (SIMO) FIR systems. The problem is to estimate the effective channel order for the SIMO system given only the output samples corrupted by noise. Two new methods for channel order estimation are presented. These methods have several useful features compared to the currently known techniques. They are guaranteed to find the true channel order for noise free case and they perform significantly better for noisy observations. These algorithms show a consistent performance when the number of observations, channels and channel order are changed. The proposed algorithms are integrated with the least squares smoothing (LSS) algorithm for blind identification of the channel coefficients. LSS algorithm is selected since it is a deterministic algorithm and has some additional features suitable for order estimation. The proposed algorithms are compared with a variety of dierent algorithms including linear prediction (LP) based methods. LP approaches are known to be robust to channel order overestimation. In this thesis, it is shown that significant gain can be obtained compared to LP based approaches when the proposed techniques are used. The proposed algorithms are also compared with the oversampled single-input, single-output (SISO) system with a generic decision feedback equalizer, and better mean-square error performance is observed for the blind setting. Channel order estimation problem is also investigated for semi-blind systems where a pilot signal is used which is known at the receiver. In this case, two new methods are proposed which exploit the pilot signal in dierent ways. When both unknown and pilot symbols are used, a better estimation performance can be achieved compared to the proposed blind methods. The semi-blind approach is especially effective in terms of bit error rate (BER) evaluation thanks to the use of pilot symbols in better estimation of channel coecients. This approach is also more robust to ill-conditioned channels. The constraints for these approaches, such as synchronization, and the decrease in throughput still make the blind approaches a good alternative for channel order estimation. True and effective channel order estimation topics are discussed in detail and several simulations are done in order to show the significant performance gain achieved by the proposed methods.

In this thesis, we study the performance of an antenna switching (AS) system in comparison to an Alamouti coded system. We analyze the outage probabilities and propose minimum mean-squared error based iterative equalizers for both systems. We see from the outage probability analysis of both systems that the AS system may achieve the same diversity order of the Alamouti coded scheme contingent on the transmission rate and constellation size. In the proposed receiver, MMSE equalization and channel decoding are jointly carried out in an iterative fashion. We use both hard and soft decision channel decoders in our simulations. It is observed that the Alamouti based scheme performs better when the channel state information is perfect. The Alamouti scheme also performs better than the AS scheme when the channel state information is imperfect in hard decision channel decoder case and a random interleaver is used. On the other hand, if a random interleaver is not used, AS scheme performs remarkably better than the Alamouti scheme in hard decision channel decoder case. In a soft decision channel decoder case, when the channel state information is imperfect, the AS scheme performs approximately a 2 dB better than the Alamouti scheme. Moreover, there is approximately a 3 dB performance gain if a soft decision channel decoder is used instead of hard decision.

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Due to the differences in batteries of a series-connected battery bank, the restored capacity in each battery may not be the same when being charged. In order to extend battery cycle life, the charger for the battery bank must have the capability of charging equalization. This thesis proposes a non-dissipative balance charging circuit based on buck-boost topology for a series-connected battery bank. Each battery in a battery bank is associated with a buck-boost converter. This topology can efficiently alleviate the unbalance of charge among batteries by taking off the charge from the affluently charged batteries and then allotting to those insufficient ones. To accomplish this complicated and accurate control, a digital signal processor (DSP) with sensors and interface circuits is adopted. It monitors the variations of battery voltages, activates the associated buck-boost converter, and adjusts the duty ratio of the converter to regulate the energy to be released. In virtue of the adoption of digital control kernel, the control circuit can be simple and the control flexibility can be favored. A battery bank with four series connected lead-acid batteries is used for illustrating the operating behavior and describing the operation modes of the balance charging circuit. The results of experiments convincingly advocate the applicability of the proposed approach.

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