Due to concerns about the negative impacts of powering vehicles using fossil fuel and the future availability of fossil fuel, there has been an increased focus on electric vehicles. However, current electric vehicle energy efficiency is a key problem as these vehicles are not as efficient as fossil-fueled vehicles. One way of decreasing a vehicle’s energy consumption is to reduce the weight of the vehicle, while still ensuring the safety and reliability of the vehicle. Controller Area Network (CAN) systems have been used in vehicles to realize real-time applications, however the low peak data rates of CAN have begun to limit the applications that can be realized. This bachelor’s thesis project focuses on secure communication within a vehicle using Ethernet. Additionally, the use of Power over Ethernet can be used for powering some of the network attached devices within the vehicle. The goal is to reduce the number of components and the weight of the vehicle while continuing to ensure the security and reliability of the communication – even when the network grows in size (either in physical size or in number of connected devices). This thesis shows that an Ethernet based system can serve as a possible replacement candidate for the CAN system due to its low latencies and high bandwidth. Ethernet is also a very scalable system with none of the limitations that a CAN system have. / Den negativa påverkan av fossila bränslen har de senaste årtionden haft en negativ på planeten, mängden fossila bränslen över världen konsumeras även i en högre takt än vad som produceras. Därför har fokusen för att finna förnybara energi källor som både är effektiva och inte påverkar miljön på ett negativt sätt ökat. Därför är elbilar en viktig del i konverteringen av enheter som drivs av fossila bränslen till förnybara energikällor. Ett av problemen i en elbil är att energi konsumptionen är inte lika effektiv som fossila bränslen inom bil industrin. Ett sätt att sänka energi konsumptionen är att minska mängden komponenter inom en bil för att minska på vikten, utan att påverka säkerheten och tillförlitligheten. Tidigare har man använt sig av ett CAN system för att försäkra sig om systemet fungerar felfritt i realtid, problematiken med detta system är att när nätverket ökar i storlek så sätter de fysiska begränsningarna av detta system stop för den garanterade säkerheten. Detta kandidatexamensarbete kommer att fokusera på den interna kommunikationen i en elbil med hjälp av ett ethernet baserat kommunkations system över CAN systemet. Power over Ethernet tekinken kommer att tillämpas för de systemen som kan drivas av detta system. Målet är att reducera antalet komponenter som behövs och att garantera säkerheten och tillförlitligheten av den interna kommunikationen när nätverket av komponenter ökar i storlek. Det här kandidatarbetet visar att Ethernet kan ersätta det nuvarande CAN systemet ef-tersom att Ethernet erbjuder låga latenser och hög bandbredd. Detta arbete visar även att Et-hernet är väldigt skalbart och har inte begränsingarna som ett CAN system har.

[pt] O objetivo desta dissertação consiste no desenvolvimento de um analisador de erro para Redes Ópticas através da utilização de circuitos integrados programáveis operando na taxa do Gigabit. As principais fontes de erro, as técnicas de medição da taxa de bits errados e a avaliação de desempenho de enlaces elétricos e ópticos em redes de telecomunicações são descritas e caracterizadas. Dispositivos de transmissão e recepção são desenvolvidos através da introdução de ferramentas computacionais para FPGA colocando-se em evidência o mecanismo de alinhamento e sincronização entre os dois. As simulações e análises destes dispositivos são apresentadas possibilitando a inserção destes em um módulo capaz de avaliar o desempenho de um enlace óptico na taxa de 1.25Gbit/s em função da taxa de bits errados. / [en] The objective of this dissertation consist on development of an error analyzer for Optical Networks by the use of programmable integrated circuits operating in Gigabit rates. The main sources of error, the techniques of BER measurement and the performance evaluation of the electric and optical links in telecommunication networks are described and characterized. Transmission and reception devices are developed through the introduction of computational tools for FPGA giving emphasis to alignment and synchronization mechanism between the two. The simulations and analyses of these devices are presented making possible the insertion of these in a module capable to evaluate the performance of the optical link in the 1.25Gbit/s rate in function of the BER.

Neste trabalho, é apresentado o desenvolvimento de um IP de rede Ethernet com interface para o barramento Avalon para utilização em conjunto com o processador Nios II da Altera. O IPC foi adaptado do projeto Ethernet_tri_mode, e é capaz de transferir dados a velocidades de 1000, 100 e 10 Mbps. O desenvolvimento envolveu a adaptação do código para atingir os requisitos do projeto, feito segundo as diretrizes do CIERMag de manter todo o código em VHDL. Além disso, foi implementada uma interface de comunicação com o processador Nios II para tornar possível a configuração do sistema, bem como a transferência de dados através de um software sendo executado no processador. O IPC Ethernet foi projetado para ser aplicado no espectrômetro digital em desenvolvimento pelo CIERMag e teve como compromissos a baixa utilização de recursos lógicos do FPGA e, ao mesmo tempo, a disponibilização de uma alta taxa de transferência de dados para o espectrômetro. Como ferramenta de desenvolvimento, foi utilizada a plataforma Quartus II cujo fornecedor é a Altera. Já os testes em placa foram realizados em um kit de desenvolvimento DE3-150 da Terasic, o qual utiliza uma FPGA Stratix III, também da Altera. Com o intuito de testar e validar o sistema, foi desenvolvido um software para o processador Nios II capaz de receber e enviar dados através do IPC e com inteligência para responder pedidos do tipo ARP e PING. O subsistema de Gigabit Ethernet desenvolvido aqui já incorpora a versão corrente do Espectrômetro Digital de RM do CIERMag. / In this work we expose the implementation of an Ethernet network core which interfaces to Avalon bus used along with the Nios II Altera processor. This core was adapted from the Ethernet_tri_mode project. It can transfer data at rates of 1000, 100 and 10 Mbps. The development involved the adaptation of the code to fullfil the project requirements, under the policy of the CIERMag to keep the whole coding in VHDL. Furthermore was implemented an interface to communicate with the Nios II processor to enable system configuration and data transfer through a software running on the processor. The core was projected to be applied with focus on the utilization of low FPGA logical resources with the availability of a high data transfer rate. It will be used in a digital spectrometer under development at the CIERMag. The Quartus II platform, supplied by Altera was used as the development tool. The tests on board where carried out on a DE3-150 development kit from Terasic, which has an FPGA Stratix III also from Altera. In order to test and validate the system, a software for the Nios II processor was developed, able to send and receive data via IPC and with intelligence to answer ARP and PING types requests. The developed Gigabit Ethernet subsystem is now part of the running version of the CIERMag Digital MR Spectrometer.

Com o crescimento acelerado da complexidade das aplicações e softwares que exigem alto desempenho, o hardware e sua arquitetura passou por algumas mudanças para que pudesse atender essa necessidade. Uma das abordagens propostas e desenvolvidas para suportar essas aplicações, foi a integração de mais de um core de processamento em um único circuito integrado. Inicialmente, a comunicação utilizando barramento foi escolhida, pela sua vantagem de reuso comparado a ponto a ponto. No entanto, com o aumento acelerado da quantidade de cores nos Systems-on-Chip (SoC), essa abordagem passou a apresentar problemas para suportar a comunicação interna. Uma alternativa que vem sendo explorada é a Network-on-Chip (NoC), uma abordagem que propõe utilizar o conhecimento de redes comuns em projetos de comunicação interna de SoC. Esse trabalho fornece uma arquitetura de NoC completa, configurável, parametrizável e no padrão Ethernet. Os três módulos básicos da NoC, Network Adapter (NA), Link e Switch, são implementados e disponibilizados. Os resultados foram obtidos utilizando o FPGA Stratix IV da Altera. As métricas de desempenho utilizadas para validação da NoC são a área no FPGA e o atraso na comunicação. Os parâmetros disponibilizados são referentes as configurações dos módulos desenvolvidos, considerando características apresentadas de aplicações DSP (Digital Signal Processing). O experimento utilizando dois NAs, dois cores e um Switch precisou de 7310 ALUTs do FPGA EP4SGX230KF40C2ES o que corresponde a 4% dos seus recursos lógicos. O tempo gasto para a transmissão de um quadro ethernet de 64 Bytes foi de 422 ciclos de clock a uma frequência de 50MHz. / With the accelerated growth of the complexity of the software and applications that require high performance, hardware and its architecture has undergone a few changes so it could meet that need. One of the proposals and approaches developed to support these applications, was the integration of more than one core processing in a single integrated circuit. Initially, the bus communication architecture was chosen, using for its reuse benefit compared to point-to-point. However, with the cores number increase in Systems-on-Chip (SoC), this approach began to present problems to support internal communication. An alternative that has been explored is the Network-on-Chip (NoC), an approach that proposes to use knowledge of common networks on internal communication projects of SOC. This dissertation focuses is to provide a complete NoC architecture, configurable, customizable and on standard Ethernet. The three NoC basic modules, Network Adapter (NA), Link and Switch, are implemented. The results were obtained using the Stratix IV FPGA. The performance metrics used for NoC validation are silicon area and latency. The available parameters are related to developed modules settings, considering features presented of DSP applications. The experiment using two NA, two cores and one Switch needed 7310 FPGA ALUTs which corresponds to 4% of their logical resources. The time for the transmission of an ethernet frame of 64 Bytes was 422 clock cycles at 50 MHz.

[pt] A presente dissertação tem como objetivo avaliar as mudanças que estão ocorrendo nas arquiteturas das redes ópticas dos operadores de telecomunicações para adequarem-se aos novos serviços oferecidos aos usuários. Esses serviços demandam cada vez mais flexibilidade, confiabilidade e capacidade de todos os níveis das redes ópticas, desde o acesso até os backbones metropolitanos e de longa distância, passando pelas redes de agregação. No acesso, a principal transformação é a extensão da fibra óptica para pontos cada vez mais próximos do usuário, utilizando-se de tecnologia PON (Passive Optical Network), de maneira a oferecer maior banda permitindo a diversificação de serviços e aplicações, como vídeo de alta definição com interatividade. No backbone metropolitano também são verificadas importantes mudanças, implicando a necessidade de capacidades de transporte cada vez maiores (múltiplos lambdas de 40 Gbps ou 100 Gbps) com uso de DWDM (Dense Wavelength Division Multiplexing) e OTN (Optical Transport Network), com roteamento de lambda no nível óptico por meio do uso de ROADM (Reconfigurable Add-Drop Multiplexer) e switching eletrônico também suportado pela OTN. Essa rede de elevada capacidade conecta-se diretamente às redes de acesso ou redes coletoras ou de agregação, aptas a transportar de forma eficiente tráfego baseado em pacotes. Nesse contexto, substituem-se as soluções tradicionais baseadas em TDM (Time Division Multiplexing) por soluções mais adaptadas ao transporte de pacotes e que garantam qualidade de serviço. Essa mesma rede de alta capacidade metropolitana também deve fazer interface com as redes de transmissão regionais e interurbanas de longa distância. O trabalho dará especial atenção às topologias de rede de acesso e backbone metropolitano descritas acima, comparando arquiteturas e investimentos associados. / [en] This dissertation aims to evaluate the changes that are occurring in the telecom operators’ optical network infrastructures to suit to the new services offered to their customers. These services demand increasingly flexibility, reliability and capacity from all optical network layers, from access to long-haul and metropolitan backbone, including aggregation layer. On access, the main transformation is the extension of the optical fiber to points closer to the customers using PON (Passive Optical Networks) technologies in order to offer higher bandwidths. With this strategy it is possible to enable applications and services diversification, like interactivity high definition video. It is also verified important changes on the metropolitan backbone. It is observed the need of improving the transport capacity (multiple 40 Gbps or 100 Gbps wavelengths) using DWDM (Dense Wavelength Division Multiplexing) and OTN (Optical Transport Network), with wavelength routing using ROADM (Reconfigurable Add-Drop Multiplexer) and electronic switching. This high-capacity network is connected directly to the access or aggregation networks, which are able to efficiently carry packet-based traffic. In this context, traditional solutions based on TDM (Time Division Multiplexing) are replaced by solutions best adapted for packet transport with reliable quality of service. This same high-capacity metropolitan network should also be connected with the regional and longhaul networks. This work will give special attention to the access network topologies and metro backbone described above, comparing architectures and related investments.

<p>Ethernet technology is being accepted by industrial community due to its open standardization </p><p>and low cost. To meet the requirements of industrial applications, a switched Ethernet </p><p>network with hard real time guarantees using relative deadlines is presented as a first step to </p><p>verify the functionality. The goal of the project was primarily to implement a real-time </p><p>switched Ethernet with EDF (Earliest Deadline First) scheduling algorithm. </p><p>In this project, the function simulations of real-time switched Ethernet with distributed control </p><p>software have been implemented, by using a standard switch with priority-queues and the </p><p>distributed software, as well as EDF-scheduled TDMA (Time Division Medium Access). The </p><p>network topology is the star type. There is no extra hardware added into the switch and the </p><p>nodes. All functions are implemented by software and the setting in the switch. </p><p>The project focuses on hard real-time service guarantees but soft real-time traffic and non </p><p>real-time traffic, as well as real time administration are also taken into the consideration. </p><p>Our simulations show that 100 percent of the network usage could be scheduled and the result </p><p>of deterministic real-time properties of the system are achieved as expected.</p>

Ethernet technology is being accepted by industrial community due to its open standardization and low cost. To meet the requirements of industrial applications, a switched Ethernet network with hard real time guarantees using relative deadlines is presented as a first step to verify the functionality. The goal of the project was primarily to implement a real-time switched Ethernet with EDF (Earliest Deadline First) scheduling algorithm. In this project, the function simulations of real-time switched Ethernet with distributed control software have been implemented, by using a standard switch with priority-queues and the distributed software, as well as EDF-scheduled TDMA (Time Division Medium Access). The network topology is the star type. There is no extra hardware added into the switch and the nodes. All functions are implemented by software and the setting in the switch. The project focuses on hard real-time service guarantees but soft real-time traffic and non real-time traffic, as well as real time administration are also taken into the consideration. Our simulations show that 100 percent of the network usage could be scheduled and the result of deterministic real-time properties of the system are achieved as expected.

The importance of real-time communication at the device level in a factory automation setup is a widely researched area. This research is an effort to experimentally verify if Ethernet can be used as a real-time communication standard in a factory automation setup, by observing the effects of packet delays, packet loss, and network congestion on the performance of a networked control system (NCS). The NCS experimental setup used in this research involves real-time feedback control of multiple plants like DC motors and a magnetic-levitation system connected to one or more controllers. A multi-client-multi-server architecture on a local area network (LAN) was developed using user datagram protocol (UDP) as the communication protocol. Key observations are as follows. (1) The multi-client-single-server system showed the highest packet delays compared to single-client-single-server architecture. (2) In the singleclient- single-server system, as the Ethernet link utilization increased beyond 82 percent, the average packet delays and steady-state error of the DC motor speed-control system increased by 2231 percent and 304 percent, respectively. (3) Even under high link utilization, adding an additional server to the NCS reduced average packet delays considerably. (4) With large packet sizes, higher packet rates were automatically throttled by Ethernet’s flow control mechanism affecting the real-time communication negatively. (5) In the multiclient- multi-server architecture, average packet delays at higher packet rates, and at higher packet lengths were found to be 40 percent lesser than the those of the single-clientsingle- server system and 87.5 percent lesser than those of the multi-client-single-server system.

Des recherches antérieures introduisent la coopétition comme stratégie d'innovation technologique dans le secteur high-tech. Jusqu'à présent, nous disposons de résultats contradictoires sur l'impact de la coopétition sur la capacité des entreprises à innover ou sur leurs positions de marché. Il est encore nécessaire d'envisager un questionnement sur au moins trois niveaux : les déterminants de la coopétition, la mise en œuvre et le management de la coopétition, les résultats de la coopétition. Comment la coopétition impacte l'innovation technologique des rivaux/partenaires? Cette question est déclinée en trois sous-questions : Qu'est-ce qui motive les entreprises à choisir la coopétition comme stratégie de R&D? Quelles formes de coopétition favorisent quels types d'innovation? Qu'est ce qui détermine les bénéfices des entreprises de la coopétition ? La première phase de recherche est de nature exploratoire où nous avons mené 15 entretiens semi-directifs. Ensuite, nous avons choisi, sur la base des résultats de la première phase, le projet 100GET comme cas d'étude. Ce projet est un projet de coopétition multiple où quatre grands concurrents européens sur le marché des solutions Ethernet ont collaboré ensemble pour développer la prochaine génération de la technologie Ethernet de 100 Gigabits. Nous avons effectué 27 entretiens semi-directifs. Nos résultats montrent que la coopétition aide les partenaires/rivaux à rendre leur technologie plus mature pour l'exploitation individuelle et l'utilisation dans leurs produits et services. Le degré de maturité de la technologie est composé de trois dimensions : une dimension marché, une dimension institutionnelle et une troisième au niveau de l'entreprise (technologique). Notre recherche montre que les différentes formes de coopétition peuvent être adaptées à différents types d'innovation. D'autre part, faire de la coopétition dyadique avec son rival « encastré » est approprié pour améliorer ou démontrer la faisabilité d'une technologie. Au niveau de l'impact de la coopétition, la recherche montre que, selon l'objectif de vitesse fixé par la firme, sa vitesse d'apprentissage dans le projet coopétitif et son choix de la stratégie de gestion de ses ressources, elle aura un impact sur la probabilité d'atteindre cet objectif. Nous avons proposé quatre modèles de la vitesse. Chacun d'entre eux est caractérisé par une vitesse, une stratégie de gestion des ressources et des coûts différents. Enfin, pour bénéficier des avantages de la coopétition, les entreprises doivent gérer efficacement les tensions liées à la coopétition. Ces tensions sont induites par la nature contradictoire de cette relation. / Previous research introduced coopetition a strategy for technological innovation in high-tech sector. Till now, we have contradictory results on the impact of coopetition on firms' capacity to innovate or market position. These results means that we still have to open the black box to understand: how coopetition impact technological innovation of rivals/partners? This research has to understand what motivates firms to choose coopetition as a strategy in R&D? What forms of coopetition favours which type of innovation? And what determine firms' benefits from coopetition? In this research, we will answer these latter questions. A research design is of two phases was conducted to answer our research questions. First phase is of exploratory nature where we conducted 15 semi-structured interviews. In the second phase we chose, based on the results of the first phase, the project 100GET as a case. This project is a multiple coopetition project where four major European competitors in the Ethernet solutions market collaborated together to develop the next generation of 100 Gigabit/s Ethernet technology. We conducted 27 semi-structured interviews. Our results show that coopetition helps rival/partners to render their technology more mature for individual exploitation and use in their product and services. The technology maturity degree is composed of: market, institutional and firm (technological) dimensions. Our research shows that different forms of coopetition could be suitable for different types of innovation, Doing multiple coopetition with unfamiliar rivals/partners' is suitable to achieve industry-wide (radical) innovation. On the other hand, doing dyadic coopetition with embedded rival/partners' is suitable to improve incrementally or to demonstrate the feasibility of a technology. At coopetition benefits side, we showed that according to firm's speed objective, firm's learning speed in coopetitive project and its choice of resource management strategy will impact its likelihood to achieve this objective. We proposed four speed patterns. Each of them is characterized by different speed, resource management strategy and costs. Finally, in order for firms to manage effectively tensions related to coopetition to ensure its benefit from coopetition, they have to manage tensions induced from the contradictory nature of this relationship. Different attentions at different organisational levels led to different results from coopetition.

Neste trabalho, é apresentado o desenvolvimento de um IP de rede Ethernet com interface para o barramento Avalon para utilização em conjunto com o processador Nios II da Altera. O IPC foi adaptado do projeto Ethernet_tri_mode, e é capaz de transferir dados a velocidades de 1000, 100 e 10 Mbps. O desenvolvimento envolveu a adaptação do código para atingir os requisitos do projeto, feito segundo as diretrizes do CIERMag de manter todo o código em VHDL. Além disso, foi implementada uma interface de comunicação com o processador Nios II para tornar possível a configuração do sistema, bem como a transferência de dados através de um software sendo executado no processador. O IPC Ethernet foi projetado para ser aplicado no espectrômetro digital em desenvolvimento pelo CIERMag e teve como compromissos a baixa utilização de recursos lógicos do FPGA e, ao mesmo tempo, a disponibilização de uma alta taxa de transferência de dados para o espectrômetro. Como ferramenta de desenvolvimento, foi utilizada a plataforma Quartus II cujo fornecedor é a Altera. Já os testes em placa foram realizados em um kit de desenvolvimento DE3-150 da Terasic, o qual utiliza uma FPGA Stratix III, também da Altera. Com o intuito de testar e validar o sistema, foi desenvolvido um software para o processador Nios II capaz de receber e enviar dados através do IPC e com inteligência para responder pedidos do tipo ARP e PING. O subsistema de Gigabit Ethernet desenvolvido aqui já incorpora a versão corrente do Espectrômetro Digital de RM do CIERMag. / In this work we expose the implementation of an Ethernet network core which interfaces to Avalon bus used along with the Nios II Altera processor. This core was adapted from the Ethernet_tri_mode project. It can transfer data at rates of 1000, 100 and 10 Mbps. The development involved the adaptation of the code to fullfil the project requirements, under the policy of the CIERMag to keep the whole coding in VHDL. Furthermore was implemented an interface to communicate with the Nios II processor to enable system configuration and data transfer through a software running on the processor. The core was projected to be applied with focus on the utilization of low FPGA logical resources with the availability of a high data transfer rate. It will be used in a digital spectrometer under development at the CIERMag. The Quartus II platform, supplied by Altera was used as the development tool. The tests on board where carried out on a DE3-150 development kit from Terasic, which has an FPGA Stratix III also from Altera. In order to test and validate the system, a software for the Nios II processor was developed, able to send and receive data via IPC and with intelligence to answer ARP and PING types requests. The developed Gigabit Ethernet subsystem is now part of the running version of the CIERMag Digital MR Spectrometer.