Thesis (M.S. in Computer Science)--Naval Postgraduate School, March 2004. / Thesis advisor(s): Curtis Blais. Includes bibliographical references (p. 49-50). Also available online.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007. / Chang, Gee-Kung, Committee Chair ; Zhou, G.Tong, Committee Member ; Copeland, John, Committee Member ; Riley, George, Committee Member ; Ingram, Mary Ann, Committee Member ; Ammar, Mostafa, Committee Member.

Thesis (Ph. D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2004. / Typescript. "A dissertation in engineering and telecommunication networking." Advisor: Ghulam M. Chaudhry. Vita. Title from "catalog record" of the print edition Description based on contents viewed Feb. 23, 2006. Includes bibliographical references (leaves 150-158) and index. Online version of the print edition.

Techn. Universiẗat, Diss., 2003--Berlin.

Protection and Control (P&C) devices requiring accurate timing within a power transmission substation are commonly synchronized by distributed Global Positioning System (GPS) receivers. However, utilities now request a timing system that is less dependent on the direct use of distributed GPS receivers, because of the reliability issue of GPS receivers. In addition, to reduce device-to-device cabling and enable interoperability among devices from multiple vendors, utilities are looking to adopt the Ethernet based IEC 61850 protocol suites to complement or replace a conventional hardwired secondary P&C system. The IEEE 1588-2008 synchronization protocol is a network based time synchronization technique which can co-exist with the IEC 61850 applications and deliver sub-microsecond timing accuracy. A number of IEC 61850 applications require seamless communication redundancy, whilst existing technologies used in a substation only recover communications tens of milliseconds after a communication failure. Alternatively, the newly released IEC 62439-3 Parallel Redundancy Protocol (PRP) and High-availability Seamless Redundancy (HSR) can achieve seamless redundancy by transmitting duplicate data packets simultaneously in various networks and this can satisfy the extremely high reliability requirements of transmission substations. Considering the benefits, a unified network integrating IEEE 1588 and IEC 62439 PRP/HSR can be foreseen in future substations, but utilities need confidence in these technologies before real deployment. Hence, it is necessary to conduct comprehensive tests on such a timing system so that better insight into the performance and limitation can be obtained. This thesis first investigates the feasibility to integrate IEEE 1588 and IEC 62439 PRP into a single Ethernet network using a simulation tool and subsequently presents how the hardware testbed is established. Meanwhile, although GPS receivers are commonly used for time synchronization in the power industry, their performance might not be fully investigated before deployment. Hence, this thesis also proposes a procedure to assess the performance in terms of long term stability and transient behaviour of a timing system merely based on GPS receivers and one based on a mixture of GPS receivers and IEEE 1588 devices. Test results indicate whichever system is used, careful design of equipment, proper installation and appropriate engineering are required to satisfy the stringent accuracy requirements for critical automation applications in power system.

Avec l’apparition des nouvelles technologies de communication, le nombre des systèmes embarqués avionique et automobile est en constante augmentation. La gestion des communications entre ces systèmes devient alors de plus en plus complexe à mettre en oeuvre dans un contexte où les contraintes temporelles et environnementales sont très fortes et où le taux d’échanges de messages en augmentation continuelle. L’utilisation optimale des réseaux pour acheminer les données tout en respectant les contraintes temporelles imposées est essentielle du point de vue de la sûreté de fonctionnement. Historiquement, pour répondre aux problématiques d’efficacité et de sûreté, les industriels ont développé une palette de réseaux embarqués dédiés à leurs applications cibles (CAN, LIN, . . . ). Ces réseaux présentaient des débits relativement faibles à un moment où un besoin croissant en bande passante se faisait ressentir. le choix d’utiliser le concept de composants dit ‘sur étagères’ (off the shelf COTS) permettait alors de pallier à ce nouveau besoin. Dans un souci de conservation des capacités des réseaux à garantir les contraintes temporelles imposées par les systèmes embarqués temps réel, les industriels ont dû adapter ce concept de composants sur étagères aux systèmes embarqués. L’intérêt de l’utilisation de ces composants est un gain non négligeable en bande passante et en poids pour des coûts de développements relativement faibles. L’introduction de ces composants nouveaux s’est faite de telle sorte que leur impact sur les standards préexistants et les systèmes connectés soit minimal. C’est ainsi que les réseaux dit ‘hétérogènes’ ont vu leur apparition. Ces réseaux constituent une hybridation entre les technologies embarquées historiques et les composants sur étagère. Ils consistent en des réseaux d’extrémité utilisant des technologies éprouvées (telles que le CAN) interconnectés via des passerelles à un réseau fédérateur (backbone) utilisant des composants sur étagères. Dès lors, le défi majeur à relever lors de l’utilisation d’un réseau fédérateur est de respecter les contraintes temporelles des applications sollicitant les différents réseaux. L’objectif est mis à mal sur les points d’interconnexion des réseaux hétérogènes (Passerelles). Ainsi l’approche principale utilisée pour le passage d’un réseau à un autre est l’encapsulation de trames. Pour atteindre l’optimalité de performance de cette technique plusieurs paramètres sont à prendre en compte tels que le nombre de trames à encapsuler, les ordonnancements utilisés, le coût en bande passante ainsi que l’impact sur les distributions de délais (gigue). Dans l’optique de préservation des performances des réseaux, l’objet de nos travaux porte sur l’étude, la comparaison et la proposition de techniques permettant l’interconnexion de réseaux hétérogènes temps réels à la fois pour des applications à faibles et à fortes contraintes temporelles. Après un état de l’art sur les réseaux temps réel, nous spécifions différentes techniques d’interconnexion de réseaux hétérogènes, puis, nous présentons une étude de cas basée sur une architecture réseau interconnectant différents bus CAN via un réseau fédérateur sans fil Wi-Fi. L’étude que nous avons menée montre, par le biais de différentes simulations, que cette architecture réseau est une bonne candidate pour la transmission de flux à contraintes temporelles faibles. Une architecture réseau interconnectant différents bus CAN via un réseau fédérateur Ethernet commuté est ensuite considérée dans une seconde étude de cas ciblant les applications à fortes contraintes temporelles. Dans un premier temps, nous prenons en compte le cas d’un réseau fédérateur Ethernet-PQSE et, dans un second temps, le cas d’Ethernet-AVB. Cette étude nous permet de montrer l’impact des différentes techniques d’interconnexion sur les délais des flux du réseau.

Diploma thesis deals with the design and implementation of control application that drives cutting machine module. Goal of application is controlling implemented module by terminal touch-panel. The thesis begins with the theoretical analysis of cutting machine and hardware description, which involves sensors, actuators, regulating elements and programmable controller. Ensued part of this thesis makes survey within industrial communication in automatization and selection of suitable software development tool. Implementation of application is carried out in practical part which describes source code samples and user interface visualization screens of touch-panel. Final part is dedicated to summary of results and possible extension.

Este trabalho apresenta o projeto, a verificação funcional e a síntese dos módulos funcionais de um comutador Gigabit Ethernet. As funções destes módulos encontramse definidas nos padrões IEEE 802.1D, IEEE 802.1Q, IEEE 802.3 e nos seguintes RFCs (Request for Comments): RFC 2697, RFC 2698 e RFC 4115. Estes módulos formam o núcleo funcional do comutador e implementam as principais funções dele. Neste trabalho quatro módulos são desenvolvidos e validados. Estes módulos foram projetados para serem inseridos na plataforma NetFPGA, formando o chamado “User Data Path”. Esta plataforma foi desenvolvida pela universidade de Stanford para permitir a prototipagem rápida de hardware para redes. O primeiro módulo chamado de “Árbitro de entrada” decide qual das portas de entrada do comutador ele vai atender, para que os quadros que ingressam por essa porta sejam processados. Este módulo utiliza um algoritmo Deficit Round Robin (DRR). Este algoritmo corrige um problema encontrado no módulo original desenvolvido na plataforma NetFPGA. O segundo módulo é o “Pesquisador da porta de saída”. O bloco principal deste módulo é o motor de classificação. A função principal do motor de classificação e aprendizagem de endereços MAC é encaminhar os quadros à suas respectivas portas de saída. Para cumprir esta tarefa, ele armazena o endereço MAC de origem dos quadros em uma memória SRAM e é associado a uma das portas de entrada. Este motor de classificação utiliza um mecanismo de hashing que foi provado que é eficaz em termos de desempenho e custo de implementação. São apresentadas duas propostas para implementar o motor de classificação. Os resultados da segunda proposta permite pesquisar efetivamente 62,5 milhões de quadros por segundo, que é suficiente para trabalhar a uma taxa wire-speed em um comutador Gigabit de 42 portas. O maior desafio foi conseguir a taxa de wire-speed durante o processo de “aprendizagem” usando uma memória SRAM externa. O terceiro módulo é o marcador de quadros. Este módulo faz parte do mecanismo de qualidade de serviço (QoS). Com este módulo é possível definir uma taxa máxima de transferência para cada uma das portas do comutador. O quarto módulo (Output Queues) implementa as filas de saída do comutador. Este módulo faz parte de plataforma NetFPGA, mas alguns erros foram encontrados e corrigidos durante o processo de verificação. Os blocos foram projetados utilizando Verilog HDL e visando as suas implementações em ASIC, baseado em uma tecnologia de 180 nanômetros da TSMC com a metodologia Semi-Custom baseada em standard cells. Para a verificação funcional foi utilizada a linguagem SystemVerilog. Uma abordagem de estímulos aleatórios restritos é utilizada em um ambiente de testbench com capacidade de verificação automática. Os resultados da verificação funcional indicam que foi atingido um alto porcentual de cobertura de código e funcional. Estes indicadores avaliam a qualidade e a confiabilidade da verificação funcional. Os resultados da implementação em ASIC amostram que os quatro módulos desenvolvidos atingem a freqüência de operação (125 MHz) definida para o funcionamento completo do comutador. Os resultados de área e potência mostram que o módulo das Filas de saída possui a maior área e consumo de potência. Este módulo representa o 92% da área (115 K portas lógicas equivalentes) e o 70% da potência (542 mW) do “User Data Path”. / This work presents the design, functional verification and synthesis of the functional modules of a Gigabit Ethernet switch. The functions of these modules are defined in the IEEE 802.1D, IEEE 802.1Q, IEEE 802.3 standards and the following RFCs (Request for Comments): RFC 2697, RFC 2698 and RFC 4115. These modules are part of the functional core of the switch and implement the principal functions of it. In this work four modules are developed and validated. These modules were designed to be inserted in the NetFPGA platform, as part of the “User Data Path”. This platform was developed at Stanford University to enable the fast prototype of networking hardware. The first module called “input arbiter” decides which input port to serve next. This module uses an algorithm Deficit Round Robin (DRR). This algorithm corrects a problem found in the original module developed in the NetFPGA platform. The second module is the classification engine. The main function of the MAC address classification engine is to forward Ethernet frames to their corresponding output ports. To accomplish this task, it stores the source MAC address from frames in a SRAM memory and associates it to one of the input ports. This classification engine uses a hashing scheme that has been proven to be effective in terms of performance and implementation cost. It can search effectively 62.5 million frames per second, which is enough to work at wire-speed rate in a 42-port Gigabit switch. The main challenge was to achieve wire-speed rate during the “learning” process using external SRAM memory. The third module is the frame marker. This module is part of the quality of service mechanism (QoS). With this module is possible to define a maximum transmission rate for each port of the switch. The fourth module (Output Queues) implements the output queues of the switch. This module is part of the NetFPGA platform, but some errors were found and corrected during the verification process. These module were designed using Verilog HDL, targeting the NetFPGA prototype board and an ASIC based on a 180 nm process from TSMC with the Semi-custom methodology based on standard cells. For the functional verification stage is used the SystemVerilog language. A constrained-random stimulus approach is used in a layered-testbench environment with self-checking capability. The results from the functional verification indicate that it was reached a high percentage of functional and code coverage. These indicators evaluate the quality and reliability of the functional verification. The results from the ASIC implementation show that the four modules developed achieve the operation frequency (125 MHz) defined for the overall switch operation. The area and power results demonstrate that the Output Queues module has the largest area and power consumption. This module represents the 92% of area (115 K equivalent logic gates) and the 70% of power (542 mW) from the User Data Path.

This thesis provides analytical and forensic tools for data cabling, with particular focus on Ethernet cabling to assist designers and those involved in deployments in analyzing cable performance and the reasons behind the actual performance obtained. The need for higher bandwidth to accommodate increasing demand for multimedia services and data centers network infrastructure led to the formation of IEEE P802.3bq to create standards for 40GBASE-T over twisted pair cables. The 40GBASE-T is expected to offer bandwidth of up to 2000MHz over a maximum channel length of 30m. The research investigated means of predicting key performance parameters in Ethernet cabling standardization using the 40GBASE-T as an example. The performance parameters prediction method provided is equally applicable to ongoing and future high data rate Ethernet cabling standardization such as the 2.5/5GBASE-T and 50/100GBASE-T. Another problem in the Ethernet networking world is the availability of counterfeit and non-standards compliant twisted pair cables in the market. The significant amount of communications cables in the market containing copper clad aluminum cable or other non-standards compliant conductors disguised as Category 6 cables can pose serious problems to companies’ networks, the contractors or the installers. This is in view of the growing demand for internet of things (IOT) services that makes it imperative to have a reliable Ethernet driven communication network to support the required infrastructure. This thesis therefore, provides techniques that can be used to evaluate cables key performance parameters using the Feature Selective Validation method and the Kolmogorov-Smirnov (KS) test. The technique can help engineers avoid subjective judgement and make objective decisions in the selection of cables. The research provided a technique that can be used to reverse engineer impedance profile from the return loss measurement of Ethernet cables using genetic algorithms. The method can be applied in situations where time domain tests are inaccessible or only simple (magnitude) tests in the frequency domain are available and there is the need for impedance profiles of cables to evaluate their performance or physical integrity before or after installation. The method can also be useful where only simple (magnitude) tests are the only historical data available for the cables and facilities for time domain reflectometry measurements are inaccessible. This research also presented a method of evaluating and predicting NEXT in unshielded twisted pair (UTP) using Category 6 cables as an example. The results obtained from the evaluation were used to provide crosstalk parameters for fast NEXT prediction in Category 6 (UTP) cables. The research used the measured NEXT of three Category 6 (UTP) cables from different manufacturers for evaluation and validation. The evaluation and modeling method can thus be useful to engineers investigating NEXT in the design of data communication systems.

Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology, 2017. / Transmission lines are a vital part of the electrical distribution system, as they provide the path to transfer power between generation and load. Factors like de-regulated market environment, economics, etc. have pushed utilities to operate transmission lines close to their operating limits. Any fault, if not detected and isolated quickly will cascade into a system wide disturbance causing widespread outages for a tightly interconnected system operating close to its limits. Current differential criterion is used with success to protect various elements in power systems, i.e. transmission lines, power transformers, generators and busbars. The alpha plane differential relaying system provides sensitive protection for transmission lines, security and dependability for external faults. This thesis focuses on three terminal alpha plane differential protection with the aim to develop a complete test method using OMICRON test universe software essentially defining security, dependability and sensitivity of the alpha plane characteristic. The research analyses the three terminal alpha plane characteristic and existing primitive test methods and develops an improved test method using IEC 61850 standard. The primitive methods are time consuming and result in unnecessary prolonged outages. These methods have been discussed and improved in the thesis by implementing IEC 61850 standard. First the standard IED Capability Description (ICD) file is modified by developing new logical nodes using AcSELerator Architect and XML Maker software. Then the developed logical nodes, three terminal differential protection alpha plane characteristic with its additional infeed/outfeed check logic, and the developed test method are tested simultaneously using Test Universe software. A laboratory test bench is built using three SEL311L relays, two CMC 356 Omicron injection devices, PC, MOXA switch, CMIRIG-B time synchronising unit, SEL 2407 satellite synchronised clock, and a DC power supplier. The test method developed in this research vindicates benefits of IEC 61850 standard over hard wired systems. Prolonged outage times due to test set preparation using hard wires are drastically reduced. The thesis findings and deliverables will be used as a solution to industrial problems, postgraduate studies of other students and research project.