The thesis gives an overview of the issue of control of full-color RGB LED panels with a large number of rows and columns. It deals with communication protocols for image transfer and information exchange. It focuses on implementing the FPGA into the RGB LED control structure. In the first half, the thesis focuses on deepening the theoretical knowledge about LED technologies, their control and color display. It further solves communication with superior elements. The last part of the theory is dedicated to FPGA circuits. The second part of the thesis describes the practical design of the FPGA circuit from UART and SPI communication through data storage from the communication to the panel control itself.

This thesis deals on the design, implementation, testing and measuring of a firmware module for FPGA chips, which enables DMA transfers of network data from computer RAM to the FPGA chip placed on a network interface card. These transfers are carried out using a PCIe bus on the speed of up to 100 Gbps with the possible support of speeds 200 Gbps and 400 Gbps. The goal of this technology is to allow network data processing for the purpose of maintenance of backbone network nodes and data centers. The module is designed so it can be used on different types of FPGA chips, mainly those produced by companies Xilinx and Intel.

The thesis is focused on designing OFDM modem, which should be implemented into the FPGA device. The advantages of using OFDM signals in order to provide high baud rates together with high multipath immunity has provoked a mass expansion into media systems such as DSL, DVB, Wi-Fi, WLAN, etc. . Thanks to this technology we can quarantee high modulation rates with minimal negative disturbance eects. The rst part is dedicated to characterise OFDM signals, their generation and the algorithm producing the OFDM which is implemented in DSP devices. For the purpose of using the fastest algorithm, the Fast Fourier Transform using Cooley-Tukey algorithm was shown. Before we can implement OFDM modem into the FPGA device, we have to simulate its correct function. Because there is no OFDM analyser available at our departement, its necessary to prove its correct function by simulations. Therefore a large part of this thesis is focused on simulations using Matlab and ModelSim, in order to show comparison between the theoretical, and simulated results. Between the theoretical and practical simulations there is a part which shows the brief characteristics of available FPGA devices. Detailed view is presented just for the Virtex II device, which the implementation is made for. As a suitable FPGA device, we have chosen Virtex II XC2V1000 which is available for students. In the last part the measured results were shown to prove the corect function of the modem. Programming the FPGA using VHDL language is realized in the software ISE Xilinx (distributed in Xilinx software support). All programmed scrits and data used in this thesis are included on distributed media.

This diploma work aims to invent an algorithm for use of serial interface SGMII (serial gigabit multimedia independent interface) in adaptive embedded data splitter for Gigabit Ethernet standard 1000Base-T interface and also to aplicate these algorithms to FPGA circuit.

Whether it's capturing a car's license plate on the highway or detecting someone's facial features to tag friends, computer vision and image processing have found their way into many facets of our lives. Image and video processing algorithms ultimately tailor towards one of two goals: to analyze data and produce output in as close to real-time as possible, or to take in and operate on large swaths of information offline. Image convolution is a mathematical method with which we can filter an image to highlight or make clearer desired information. The most popular uses of image convolution accentuate edges, corners, and facial features for analysis. The goal of this project was to investigate various image convolution algorithms and compare them in terms of hardware usage, power utilization, and ability to handle substantial amounts of data in a reasonable amount of time. The algorithms were designed, simulated, and synthesized for the Zynq-7000 FPGA, selected both for its flexibility and low power consumption.

In this work a new technique for accelerating the aging of FPGA devices is proposed and demonstrated. The proposed technique uses harmful configurations (short circuits) to accelerate the aging process on targeted portions of an FPGA chip. A testbed is developed for the purpose of measuring FPGA degradation. Using this testbed it is shown that implementing thousands of short circuits in FPGA fabric generates enough heat to cause significant damage to the chip, reducing switching speeds by up to 8%. It is also demonstrated that different parts of the FPGA fabric can be aged at different rates, with some parts of the chip only slowing down 2% while other parts slowdown as much as 8%.

Indiana University-Purdue University Indianapolis (IUPUI) / In autonomous driving, medical diagnosis, unmanned vehicles and many other new technologies, the neural network and computer vision has become extremely popular and influential. In particular, for classifying objects, convolutional neural networks (CNN) is very efficient and accurate. One version is the Region-based CNN (RCNN). This is our selected network design for a new implementation in an FPGA. This network identifies stop signs in an image. We successfully designed and trained an RCNN network in MATLAB and implemented it in the hardware to use in an embedded real-world application. The hardware implementation has been achieved with maximum FPGA utilization of 220 18k BRAMS, 92 DSP48Es, 8156 FFS, 11010 LUTs with an on-chip power consumption of 2.235 Watts. The execution speed in FPGA is 0.31 ms vs. the MATLAB execution of 153 ms (on the computer) and 46 ms (on GPU).

The Field Programmable Gate Array (FPGA) is a platform with a unique set offeatures. It combines the programmability of general purpose computers with the flexibility of Application Specific Integrated Circuits (ASIC). Most basic operations have been thoroughly studied on ASICs and the best architecture for each operation has often been found. This is not the case for FPGAs where often it is just assumed that the best architecture for an operation is the same in a FPGA as in a ASIC. As FPGAs have unique features and restrictions compared to ASICs this assumption is not always right. In this thesis, divider- and interpolation-architectures have been studied and modified to fit better on the FPGA platform. To do this a base design from the ASIC world was taken and studied to look for things that can be improved for the FPGA platform. These changes were then simulated and tested on four different FPGA-chip series for a wide range of bit lengths. For the divider architecture, it was found that the non-restoring divider design performed the best. For the interpolation architecture, some interesting ideas on how to save hardware was found but no real conclusion can be reached about which design is better than the others.

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