Made available in DSpace on 2014-06-11T19:27:12Z (GMT). No. of bitstreams: 0 Previous issue date: 2011-12-16Bitstream added on 2014-06-13T19:35:01Z : No. of bitstreams: 1 dias_gcb_me_guara.pdf: 1781054 bytes, checksum: 9aebafdc1f0f4dac5ad0f6b86d3c63ff (MD5) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / O presente trabalho estudou as variáveis de fabricação no processo na linha de galvanização contínua por imersão a quente, simulando o processo de conformação e a cura da pintura nas montadoras, visando avaliar as condições de deformação, tempo, temperatura e o envelhecimento desde o tempo de estocagem até a conformação dos aços ultra baixo carbono semi-estabilizado ao Nióbio para obtenção de índices de bake hardening (IBH) satisfatórios, visando o atendimento e a garantia das especificações dos aços BH180 e BH220. Para a execução das análises, utilizou-se o laboratório de controle da qualidade da empresa, onde foram retirados corpos de prova para ensaios de tração e do índice bake hardening seguindo os procedimentos conforme a norma requisitada. O ensaio padrão de bake hardening (BH) consiste em, deformar o corpo de prova até 2%, interromper o ensaio, aquecer o material na estufa por 20 minutos a 170ºC e após resfriamento, dar continuidade ao ensaio. O cálculo do índice de BH foi especificado segundo a norma DIN BS EN 10325. Este trabalho visou a comparação entre dois testes de envelhecimento, um em condição natural e outro artificial. Na condição natural, os corpos de prova foram deixados em temperatura ambiente durante o período de seis meses e, na condição artificial, as variáveis tempo e temperatura foram analisadas. A garantia do tempo de estocagem está sendo discutida entre as montadoras e as usinas. A condição padrão para a simulação do ensaio de aços bake hardening, avaliou a influência de cada variável e verificou que o índice de BH está dentro do especificado em norma, sendo encontrado o valor de 49,0 MPa para o aço BH180 e de 45,0 MPa para o aço BH220. As variáveis mencionadas são importantes para o incremento do índice de BH principalmente a pré-deformação... / This paper studied the variables in the manufacture process in continous hot dipped galvanizing line, simulating the process of drawing and curing of paint in the automakers, to evaluate the conditions of deformation, temperature, time and aging from storage time to drawing of ultra low carbon steel semi-stabilized to achieve a reasonable bake hardening index (BH) in order to find the specifications and warranty BH180 and BH 220 steels. For the application of tests, it was use the quality control laboratory of the company`s, where specimens were removed for tensile tests and bake hardening index (BH) following the standard procedures as required. The bake hardening (BH) pattern test consists of deforming the specimen until 2%, stop the test, after heating the material in an oven for 20 minutes at 170 ° C and after air cooling, continue the trial. The calculation of a reasonable bake hardening index (BH) was specified according to DIN BS EN 10325. This study aimed to compare two aging tests, one in natural and the other one in artificial condition. In natural condition, the specimens were left at room temperature for a period of six months, and in artificial condition, time and temperature variables were analyzed. The warranty of the storage time is being discussed between the automakers and steel plants. The default condition for the simulation of the bake hardening steels test, evaluated the influence of each variable and found out that bake hardening index (BH) is within the specified standard, and with values of 49.0 MPa for BH180 steel and 45.0 MPa for BH220 steel. The variables mentioned are important for increasing the bake hardening index (BH) mainly pre-deformation has a significant influence. The steels studied seem not to have great influence on aging after the production in the time period evaluated.

Au cours des dernières années, un développement continu a été observé dans les domaines des systèmes électroniques et des ordinateurs. Une série de mécanismes menaçant la fiabilité ont émergé. Par exemple, des défauts physiques provenant de fils mal lithographié, vias et d'autres dispositifs de bas niveau sont fréquemment observées dans les circuits nanométriques. D'autre part, les circuits sont également devenus plus sensibles aux grèves de particules excitées. Ces deux mécanismes, bien que essentiellement différente, peuvent causer de multiples fautes qui contribuent pour fiabilités plus faibles dans les circuits intégrés. Fautes multiples sont plus inquiétant que de simples car elles sont plus graves et aussi parce qu'ils peuvent surmonter les techniques de tolérance aux fautes. Les circuits numériques sont utilisés dans la plupart des systèmes électroniques aujourd'hui, mais il y a un contexte spécifique dans lequel ils doivent être fiable. Tel contexte comprend des applications de haute dépendabilité. Et cela est le scénario dans lequel cette thèse est conçu. Il a un double objectif: (a) de proposer des méthodes pour évaluer la fiabilité des circuits numériques, et (b) de proposer des techniques d'amélioration de la fiabilité. En ce qui concerne le premier objectif, plusieurs méthodes ont été proposées dans la littérature et le texte montre comment ces méthodes présentent des limitations en ce qui concerne la taille de circuit (nombre de portes), le type de circuit (séquentielle ou combinatoire) et le profil de faute (unique ou fautes multiples). Cette thèse propose deux méthodes pour l'évaluation de la fiabilité. La première méthode est appelée SPR+ et elle vise l'analyse de la logique combinatoire seulement. SPR+ améliore la précision de l'analyse, en tenant compte de l'effet de chaque nœud de fanout par rapport à la fiabilité de l'ensemble du circuit. Une autre méthode, appelée SNaP, est également proposé dans cette thèse. Il s'agit d'une approche hybride, car il est partiellement basée sur la simulation. SNaP peut être utilisé pour la logique combinatoire et séquentielle, et peut également être émulé dans un dispositif FPGA pour une analyse plus rapide. Les deux méthodes, SPR+ et SNAP, peuvent traiter de fautes multiples. / With the current advances achieved in the manufacturing process of integrated circuits, a series of reliability-threatening mechanisms have emerged or have become more prominent. For instance, physical defects originating from poorly lithographed wires, vias and other low-level devices are commonly seen in nanometric circuits. On the other hand, circuits have also become more sensitive to the strikes of highly energized particles. Both mechanisms, although essentially different, can cause multiple faults that contribute for lower reliabilities in integrated circuits. Multiple faults are more troubling than single faults since these are more severe and also because they can overcome fault tolerance techniques. Digital circuits are used in most electronic systems nowadays, but there is a specific context in which they are required to be reliable. Such context comprises high-dependability applications. This is the scenario in which this thesis is conceived. It’s goals are twofold : (a) to pro pose methods to assess the reliability of digital circuits, and (b) to propose techniques for reliability improvement. Concerning the first goal, several methods have been proposed in the literature and the text shows how these methods present limitations with respect to circuit size (number of gates), circuit type (sequential or combinational) and fault profile (single versus multiple faults). This thesis proposes two methods for reliability assessment. The first method is termed SPR+ and its targeted at the analysis of combinational logic only. SPR+ improves the average analysis accuracy by taking into account the effect of each fanout reconvergent node to the overall circuit reliability. Another method, termed SNaP, is also proposed in this thesis. It is a hybrid approach since it is partially based on simulation. SNaP can be used for combinational and sequential logic and can also be emulated in an FPGA device for faster analysis. Both SPR+ and SNaP can cope with multiple faults.

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¡@In this study, the plastic deformation of (001) single crystal silicon at 900 oC is investigated by uniaxial compression along [001]. Using optical microscopy and scanning electron microscopy to observe the sample surface, and analysis the corresponding microstructure of different strain deformed silicon by transmission electron microscopy, particularly dislocation, slip systems and work hardening behaviour. ¡@Experimental temperature condition was chosen which over the BDT temperature range of silicon. We were found similar stages of work hardening described in metals and use the result of analysis dislocations and slip systems to suggest a hardening process of plastic deformation. ¡@The observations are similar to the feature in stage II (dislocation tangled) and stage III (dislocation cell structure). Partial dislocation and dipole are formed in less strained sample. We suggest a hardening process of plastic deformation from these results.

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Stress relaxation measurements were carried out on a plain carbon and four Ti steels over the temperature range 850 to 1050$ sp circ$C. The results show that the stress relaxation of plain carbon austenite after a 5% prestrain can be described by the relation $ sigma$ = $ sigma sb0$-$ alpha$ln(1 + $ beta$t). By contrast, in the solution-treated Ti steels, relaxation is arrested at the start of precipitation and is resumed when precipitation is complete. As a result, this new mechanical method is suitable for following carbonitride precipitation in microalloyed austenite at hot working temperatures. / PTT diagrams were determined by the present technique for the steels containing 0.05, 0.11, 0.18 and 0.25% Ti. The PTT curves obtained are C shaped for all the steels. The upper parts of these curves are shifted to significantly longer times as the Ti and C concentrations are reduced. By contrast, the positions of the lower arms of the curves are relatively independent of the current values of the solubility product (Ti) (C). This phenomenon is attributed to the catalytic effect of trace amounts of dissolved N on the nucleation rate of Ti(CN) in austenite. / Changes in the size distribution and morphology of the precipitates during relaxation of the 0.25% Ti steel were followed by means of electron microscopy. The cube shaped Ti(CN) precipitates were heterogeneously distributed in either a chain-like or a cell-like manner. Electron microanalysis was additionally carried out to determine the compositions of the Ti carbosulphide-Mn sulphide inclusions. / Finally, the experimental results are compared with the predictions of classical nucleation theory and of the diffusion controlled particle growth theory. Good agreement was obtained between the predictions of the theories and the experimental results. It is demonstrated by means of the thermodynamic analysis of nucleation that the Ti(CN) precipitate/austenite interface is of a semi-coherent nature. It is shown that the interface between a critical nucleus and the matrix can be characterized by the newly introduced coherency loss parameter C.