Au sein de la course industrielle à la miniaturisation et avec l’augmentation des exigences technologiques visant à obtenir plus de performances sur moins de surface, la fiabilité des transistors MOSFET est devenue un sujet d’étude de plus en plus complexe. Afin de maintenir un rythme de miniaturisation continu, des nouvelles architectures de transistors MOS en été introduite, les technologies conventionnelles sont remplacées par des technologies innovantes qui permettent d'améliorer l'intégrité électrostatique telle que la technologie FDSOI avec des diélectriques à haute constante et grille métal. Malgré toutes les innovations apportées sur l’architecture du MOS, les mécanismes de dégradations demeurent de plus en plus prononcés. L’un des mécanismes le plus critique des technologies avancées est le mécanisme de dégradation par porteurs chauds (HCI). Pour garantir les performances requises tout en préservant la fiabilité des dispositifs, il est nécessaire de caractériser et modéliser les différents mécanismes de défaillance au niveau du transistor élémentaire. Ce travail de thèse porte spécifiquement sur les mécanismes de dégradations HCI des transistors 28nm FDSOI. Basé sur l’énergie des porteurs, le modèle en tension proposé dans ce manuscrit permet de prédire la dégradation HC en tenant compte de la dépendance en polarisation de substrat incluant les effets de longueur, d’épaisseur de l’oxyde de grille ainsi que l’épaisseur du BOX et du film de silicium. Ce travail ouvre le champ à des perspectives d’implémentation du model HCI pour les simulateurs de circuits, ce qui représente une étape importante pour anticiper la fiabilité des futurs nœuds technologiques. / As the race towards miniaturization drives the industrial requirements to more performances on less area, MOSFETs reliability has become an increasingly complex topic. To maintain a continuous miniaturization pace, conventional transistors on bulk technologies were replaced by new MOS architectures allowing a better electrostatic integrity such as the FDSOI technology with high-K dielectrics and metal gate. Despite all the architecture innovations, degradation mechanisms remains increasingly pronounced with technological developments. One of the most critical issues of advanced technologies is the hot carrier degradation mechanism (HCI) and Bias Temperature Instability (BTI) effects. To ensure a good performance reliability trade off, it is necessary to characterize and model the different failure mechanisms at device level and the interaction with Bias Temperature Instability (BTI) that represents a strong limitation of scaled CMOS nodes. This work concern hot carrier degradation mechanisms on 28nm transistors of the FDSOI technology. Based on carrier’s energy, the energy driven model proposed in this manuscript can predict HC degradation taking account of substrate bias dependence (VB) including the channel length effects (L), gate oxide thickness (TOX) , back oxide BOX (TBox) and silicon film thickness (TSI ). This thesis opens up new perspectives of the model Integration into a circuit simulator, to anticipate the reliability of future technology nodes and check out circuit before moving on to feature design steps.

This thesis is concerned with the influence of nanoscale boundaries and interfaces upon the electronic processes that occur within the inorganic semiconductors. Inorganic semiconductor nanowires and their blends with semiconducting polymers have been investigated using state-of-the-art ultrafast optical techniques to provide information on the sub-picosecond to nanosecond photoexcitation dynamics in these systems. Chapters 1 and 2 introduce the theory and background behind the work and present a literature review of previous work utilising nanowires in hybrid organic photovoltaic devices, revealing the performances to date. The experimental methods used during the thesis are detailed in Chapter 3. Chapter 4 describes the crucial roles of surface passivation on the ultrafast dynamics of exciton formation in gallium arsenide (GaAs) nanowires. By passivating the surface states of nanowires, exciton formation via the bimolecular conversion of electron-hole plasma can observed over few hundred picoseconds, in-contrast to the fast carrier trapping in 10 ps observed in the uncoated nanowires. Chapter 5 presents a novel method to passivate the surface-states of GaAs nanowires using semiconducting polymer. The carrier lifetime in the nanowires can be strongly enhanced when the ionization potential of the overcoated semiconducting polymer is smaller than the work function of the nanowires and the surface native oxide layers of nanowires are removed. Finally, Chapter 6 shows that the carrier cooling in the type-II wurtzite-zincblend InP nanowires is reduced by order-of magnitude during the spatial charge-transfer across the type-II heterojunction. The works decribed in this thesis reveals the crucial role of surface-states and bulk defects on the carrier dynamics of semiconductor nanowires. In-addition, a novel approach to passivate the surface defect states of nanowires using semiconducting polymers was developed.

The objective of this work is to provide a comprehensive analysis of the small-signal and broadband noise performance of highly scaled silicon-based field-effect transistors (FETs), and develop high-frequency noise models for robust radio frequency (RF) circuit design. An analytical RF noise model is developed and implemented for scaled Si-CMOS devices, using a direct extraction procedure based on the linear two-port noise theory. This research also focuses on investigating the applicability of modern CMOS technologies for extreme environment electronics. A thorough analysis of the DC, small-signal AC, and broadband noise performance of 0.18 um and 130 nm Si-CMOS devices operating at cryogenic temperatures is presented. The room temperature RF noise model is extended to model the high-frequency noise performance of scaled MOSFETs at temperatures down to 77 K and 10 K. Significant performance enhancement at cryogenic temperatures is demonstrated, indicating the suitability of scaled CMOS technologies for low temperature electronics. The hot-carrier reliability of MOSFETs at cryogenic temperatures is investigated and the worst-case gate voltage stress condition is determined. The degradation due to hot-carrier-induced interface-state creation is identified as the dominant degradation mechanism at room temperature down to 77 K. The effect of high-energy proton radiation on the DC, AC, and RF noise performance of 130 nm CMOS devices is studied. The performance degradation is investigated up to an equivalent total dose of 1 Mrad, which represents the worst case condition for many earth-orbiting and planetary missions. The geometric scaling of MOSFETs has been augmented by the introduction of novel FET designs, such as the Si/SiGe MODFETs. A comprehensive characterization and modeling of the small-signal and high-frequency noise performance of highly scaled Si/SiGe n-MODFETs is presented. The effect of gate shot noise is incorporated in the broadband noise model. SiGe MODFETs offer the potential for high-speed and low-voltage operation at high frequencies and hence are attractive devices for future RF and mixed-signal applications. This work advances the state-of-the-art in the understanding and analysis of the RF performance of highly scaled Si-CMOS devices as well as emerging technologies, such as Si/SiGe MODFETs. The key contribution of this dissertation is to provide a robust framework for the systematic characterization, analysis and modeling of the small-signal and RF noise performance of scaled Si-MOSFETs and Si/SiGe MODFETs both for mainstream and extreme-environment applications.