Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance.

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With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher interconnections densities. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches. Other approaches such as compliant interconnects require lengthy connections and are limited in terms of electrical properties. A novel chip-package interconnection technology is developed to address the IC packaging requirements and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. This thesis investigates the electrical and mechanical performance of nano-structured interconnections through modeling and test vehicle fabrication. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.

The Wafer Level Chip Scale Package (WLCSP) is gaining popularity for its performance and ability to meet the miniaturization requirements of portable consumer electronics, such as cell phones. For the industry of electronic package, the package life of electronic products is deemed as the essential consideration in the operation period. In practice, electronic products are usually damaged due to a harsh mechanical impact, such as drop and bending. The solder interconnections provide not only the electronic path between electric components and printing circuit board, but also the mechanical support of components on the printing circuit board, so that the reliability of solder interconnection becomes an essential consideration for a package. In the thesis several parameters, including redistribution layer (RDL) material and thickness, passivation material and thickness, under-bump metallization (UBM) structure factors are discussed. A variety of WLCSP structures are investigated for solder joint reliability performance. In addition to the fatigue lives of the test vehicle, locations and modes of fractured solder joints were observed. It was found that wafer level packaging structure under drop clearly related with the characteristic life. The weakest point of solder ball was intermetallic compound (IMC), and wafer level packaging structure was the crack into the second passivation layer and UBM interface of the corner. WLCSP under temperature cycling test was done and observed the fracture only occurred at the solder ball near the package.

Since reformed of banking structure in China, banks have been gradually developed their operation system. Moreover, the restructure in commercial bank after joined WTO had established China¡¦s banks performance and international reputation. Since 2007, many large commercial banks have strength its risk management based on the commitments made by China Banking Regulatory Commission (CBRC) to follow the New Basel Capital Accord. When the global banking industry is devastated by global financial crisis (GFC) during 2008, China¡¦s banks are less affected by GFC. In addition, the capital scale and revenues performance were thrived during GFC. Therefore, it shows that banks in China had improved the resilience ability during financial crisis. However, being originated in China¡¦s loose monetary policy and economic stimulus package after GFC, investors worried that domestic banks might bear high risks. Notably, the risk is specific risk from each bank instead of system risk. This study employs Markov regime-switching model to examine 14 China banks¡¦ stock prices. The empirical evidence supports our hypothesis that behavior of China banks¡¦ stock prices has confronted structural change after GFC. Furthermore, this research presents that unsystematic risks from each bank were significantly decreased after GFC. It indicates that investors are too pessimistic on the banks in China might suffer high risk after government interventions.

Currently the trend of electronic product development is to ward ¡§light and thin, multi-functional, high density and durability¡¨. When the microelectronic chips tend to be high power, high density and high speed, the rapid increase of heat in a reduced unit area of package size, will lead to failure of electronic products. The contents of thesis is to find out the dominant factors in heat transfer by changing the geometries and material properties of QFN and BGA packages. It also aims to achieve the beat the thermal performance by reducing the probability of failure. In industries it needs a lot of cost and time in experiment work due to the changes of size and materials. Herein, the softwares of ANSYS and ICEPAK are adopted to model the QFN and BGA packages with the statistical experimental design of Taguchi method L18 (21¡Ñ37) orthogonal array setting parameters and obtain the degree of effect for each factor. Eventually, we use the analysis of variance ANOVA to obtain the contribution of each factor and to identify the significant degree for various parameters by variance error integration. From the results the die attach thermal conductivity affects the contribution of thermal performance up to 81.46% for QFN package in comparison with other controlling factors of high significance and high impact effects. Die attach thermal conductivity between 0.5 W/m•k and 1.5 W/m•k the Tj declines much larger than that between 1.5 W/m•k and 8 W/m•k. Die /PKG area ratio affects the contribution of the thermal performance to 64.24% and increasing Die /PKG area ratio can reduce the Tj for BGA package. The significant effect is also higher than other factors. However, the contribution of substrate layers is 18.83% at 99% confidence level.

Seven empirical equations were developed for the prediction of seal strength for medical device trays. A new methodology was developed and used for identifying burst and peel locations and comparing burst pressure and peel force. Multiple linear regression was used to fit 76 models, selecting the best models based on the Akaike Information Criterion (AIC) and adjusted R2 (R2 adj) value of each model. The selected models have R2 adj and prediction R2 (R2 pred) values of .83 to .94. Factors investigated for the peel force response were sealing pressure (3 levels), dwell time (3 levels), sealing temperature (3 levels), and adhesive. Additional factors investigated for the burst pressure response were restraining plate gap, and tray volume, height, length-to-width ratio and area. Polyethylene terephthalate-glycol (PETG) trays with Tyvek 1073B lids and two popular water-based adhesives were used. Trays were selected to yield three levels of area and three levels of length-to-width ratio, defining nine package configurations. Packages for burst testing were sealed under a fractional factorial design with 27 treatments. Packages for peel testing were sealed under a 17-point face-centered central composite design. Packages were tested using peel testing following the ASTM F88-07 standard and restrained burst testing with three gap distances following the ASTM F2054-00 standard. All possible subsets of the factors were evaluated, with the best models selected based on AIC value. Equations were developed to predict peak and average peel force based on sealing process parameters (R2 pred =.94 and .92), burst pressure based on tray and sealing parameters and gap (R2 pred =.94), and four peel force responses based on burst pressure and gap (R2 pred =.83 to .86). Models were validated through cross-validation, using the prediction error sum of squares (PRESS) statistic. The R2 pred was calculated to estimate the predictive ability of each model.

The focus of this study is mono-layer polymer light emitting diode (PLED). The emitting layer is poly-p-phenylenebenzobisoxazole (PBO). PBO is a fully conjugated heterocyclic aromatic rigid-rod polymer. Anode is indium-tin-oxide (ITO). Cathode is aluminum (Al). We used UV epoxy resin to package PLED devices, then measured current-voltage response, electroluminescence (EL) emission, and device lifetime. We demonstrate that the packaged mono-layer PBO LED reduced its demise from water and oxygen. Device lifetime increased from 1 hour to several hundred hours. At a larger bias voltage or current, emission intensity and device efficiency became higher. But decay rate increased leading to shortened device lifetime. Device temperature appeared linearly with current density. A red shift of the EL emission was observed. The £fmax. of emission spectra moved from 534 nm (initial) to 582 nm (after 100 hrs). After thermal annealing at 120¢J for ten hours, threshold voltage increased from 5 V to 12 V, current density decreased to several 10 mA/cm2, luminous intensity improved several ten times to 10-2 cd/m2, emission color changed from yellow-green to orange, luminous efficiency improved from 10-7 to 10-4 cd/A, but device lifetime declined to less than 20 hrs.

Because most of Taiwan semiconductor industry are (OEM; Original Equipment Manufacturer) and the major customers have two type: One is IDM which has own IC design, fab manufacturing, IC assembly and IC test, for example IBM,Inter¡Ketc.And the other is IC design houses which only have IC design, and let fab manufacturing, IC assembly and IC test outsourcing, for example Media Tek, Etron...etc. In order to force on core technology, the company¡¦s strategy is outsourcing and the outsourcing capacity will release to subcontractors. How to increase new package development performance is the major points to make sure subcontractors can get outsourcing capacity and it also can let company transfer from OEM to ODM. New package development is the basic procedure and the core technology in the semiconductor industry. Due to the product become high risk, shorter life cycle time and faster technology innovation, it causes the company will be more competitive in the world. In order to keep growth, it¡¦s very important to make sure the success of new package development. That¡¦s reason why more and more company involve customers knowledge in the new package development to reduce uncertainty, shear financial risk and provide the key decision. Believe in the customer knowledge management, customer characteristic and market information are all affect the new product development performance.

International tourist hotel industry has becoming a professional management domain nowadays. Due to the increasingly fierce competition, hotels must develop ways to attract customers by meeting their market requirements and preferences, rather than waiting passively for the customers to come. With data mining technology, the hotels can facilitate the discovered characteristics of potential customers to make the right marketing strategies and decisions by targeting at specific groups of customers. Behind the consumers¡¦ behaviors, there are usually indicators for special consuming requirements. However, by browsing the business transaction data, one can usually learn only the consuming requirement volume and is unable to determine the implied and hidden information. This research makes use of data mining technology to explore the customers¡¦ historical data. Specifically, it applies the discovered decision rule to investigate and validate the characteristics of potentially customers ¡X customers who are more likely to book rooms of higher rate. We apply the data mining techniques to the transactional data of a hotel, collected over three years. Our research reveals that there exist characteristics rules for the potential customers and these rules do not change abruptly over the years. The application of these rules to target advertising in hotel domain is verified using the hotel transaction data collected in the subsequent year. The result shows that by targeting at customers of the discovered characteristics rules, higher response rate can be achieved.