This thesis presents Hardware Join Java as a language for specification of parallel reconfigurable computing applications. Hardware Join Java is an extension of the Join Java language with added support for hardware specification. It attempts to increase the level of abstraction offered as compared to other hardware description languages (HDLs); by allowing algorithms in hardware to be expressed in the same way as in software. By incorporating the Join extension to Java, it also unifies the specification of concurrency between hardware and software.

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 127-133). Available also in a digital version from Dissertation Abstracts.

This thesis presents Hardware Join Java as a language for specification of parallel reconfigurable computing applications. Hardware Join Java is an extension of the Join Java language with added support for hardware specification. It attempts to increase the level of abstraction offered as compared to other hardware description languages (HDLs); by allowing algorithms in hardware to be expressed in the same way as in software. By incorporating the Join extension to Java, it also unifies the specification of concurrency between hardware and software.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2008. / Includes bibliographical references (leaves 37). Also available in electronic version.

Thesis (M.Sc.). / Written for the School of Computer Science. Title from title page of PDF (viewed 2008/01/16). Includes bibliographical references.

Thesis (M.S.C.I.T.)--Regis University, Denver, Colo., 2005. / Title from PDF title page (viewed on Dec. 28, 2005). Includes bibliographical references.

Thesis (M. Sc.)--Carleton University, 2001. / Includes bibliographical references (p. 111-116). Also available in electronic format on the Internet.

Yu Chun-Pong. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 60-61). / Abstracts in English and Chinese. / Abstract of this thesis entitled: --- p.i / 摘要 --- p.iii / Acknowledgements --- p.iv / Table of contents --- p.v / List of Tables --- p.vi / List of Figures --- p.vii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Asynchronous design --- p.1 / Chapter 1.2 --- Java processor for contactless smart card [3] --- p.2 / Chapter 1.3 --- Motivation --- p.3 / Chapter Chapter 2 --- Asynchronous circuit design techniques --- p.5 / Chapter 2.1 --- Overview --- p.5 / Chapter 2.2 --- Handshake protocol --- p.5 / Chapter 2.3 --- Asynchronous pipeline --- p.7 / Chapter 2.4 --- Asynchronous control elements --- p.9 / Chapter Chapter 3 --- Asynchronous Java Processor --- p.15 / Chapter 3.1 --- Instruction Set --- p.15 / Chapter 3.2 --- Architecture of the java processor --- p.17 / Chapter 3.3 --- Basic building blocks of the java processor --- p.22 / Chapter 3.4 --- Token flow --- p.32 / Chapter Chapter 4 --- Results and Discussion --- p.37 / Chapter 4.1 --- Simulation Results of test programs --- p.37 / Chapter 4.2 --- Experimental result --- p.41 / Chapter 4.3 --- Future work --- p.42 / Chapter Chapter 5 --- Conclusion --- p.45 / Appendix --- p.47 / Chip micrograph for the java processor core --- p.47 / Pin assignment of the java processor --- p.48 / Schematic of the java processor --- p.52 / Schematic of the decoder --- p.54 / Schematic of the Stage2 of the java processor --- p.55 / Schematic of the stack --- p.56 / Schematic of the block of the local variables --- p.57 / Schematic of the 16-bit self-timed adder --- p.58 / The schematic and the layout of the memory cell --- p.59 / Reference --- p.60

No description available.

Thesis (M.S. in)--Naval Postgraduate School, June 2004. / Thesis advisor(s): Matt Carlyle. Includes bibliographical references (p. 29). Also available online.