Cryptographic algorithms, like the Advanced Encryption Standard, are frequently used in todays electronic appliances. Battery operated devices are increasingly popular, creating a demand for low energy solutions. As a microcontroller is incorporated in virtually all electronic appliances, the main objective in this thesis is to evaluate possible hardware implementations of AES and implement a solution optimized for low energy consumption, suited for incorporation in a microcontroller. A good cost/performance balance is also a design goal. An existing solution based on a 32 bit architecture with support for 128 bit keys was chosen as a basis and altered in order to lower area and energy consumption. The alterations yielded a 13.6% area reduction as well as 14.2% and 3.9% reduction in energy consumption in encryption and decryption mode, respectively. In addition to alterations in the datapath, low energy techniques like clock gating and numerical strength reduction has been applied in order to further lower the energy consumption. The proposed architecture was also extended in order to accommodate 256 bit keys. Although this increased the area by 9.2%, the power consumption was still reduced by 7.6% and 1.3% in en- and decryption, compared to the architecture chosen as basis. As AES is an algorithm which easily can be parallelized, a high throughput solution utilizing a 128 bit datapath was implemented. This AES module is able to process 372.4 Mbps at an operating frequency of 32 Mhz and is based on the same architecture as the 32 bit datapath solution. In addition, this implementation yielded excellent energy per encryption figures, 24.5% lower than the 32 bit solution. The alternative to performing AES in a dedicated hardware module is to perform it using software. In order to have a basis for comparison, a software solution optimized for 32 bit architectures was implemented. Simulations show that the energy consumption attained when performing AES in the proposed hardware module is approximately 2.3% of what a software solution would use. In addition, the throughput is increased by a factor of 25. The architecture proposed in this thesis combines relatively high throughput with modest demands to area and low energy per encryption.

This report describes the assessment and design of a 10 dBm 2.4 GHz CMOS PA including driver stage. The PA is designed in a 0.18 um CMOS technology. A three stage PA has been designed due to the high voltage gain needed. Class F has been chosen for the output stage. An output filter short-circuiting the second harmonic frequency and reflecting the third harmonic frequency is used to obtain the near-square drain voltage that is characteristic to class F. A lowered supply voltage of 0.9 V is used to avoid exceeding the transistor break-down voltage of 2 V. The typical output power achieved is 10.2 dBm. The drain efficiency of the output stage is 47.7 %, and the PAE of the entire PA is 30.5 %. The final layout excluding bonding pads consumes an area of 0.66 mm2, including four internal inductors consuming a total of 0.59 mm2. The PAE obtained is higher than those of a selection of recently published PAs that are comparable in technology, frequency and output power.

This paper reports on the modeling and simulation of a continuous-time delta-sigma analog to digital converter (ADC) in VHDL AMS. The ADC is intended for use in a microcontroller and is therefore underlying restrictions on power consumption. Continuous-time delta-sigma architectures are well known for their good low-power capabilities compared to discrete-time realizations. This is due to their reduced demands to the gain bandwidth product (GBW) of the internal amplifiers in the ADCs. Continuous-time ADCs often operate with GBWs in the range of the sampling frequency, fs. The ADC presented in this work is also employing a previously reported compensation technique which ideally allows the GBW to be reduced further >20 times of this. Considering that the current drain in the amplifiers usually is proportional with GBW, this could be a promising power saving technique. The work focuses on the development of two similar models of a 2-order continuous-time delta-sigma ADC in VHDL-AMS, where one of the ADCs is using the compensation technique. The main purpose is to see how the compensated ADC is affected by nonidealities such as GBW-variation, finite amplifier gain, RC-product variation, excess loop delay and finite DAC slew rate compared to the performance of the noncompensated ADC. The required accuracy for the modeled ADCs is 62dB Signal to Noise and Distortion Ratio (SNDR), thus an appropriate oversampling ratio (OSR) also must be found. The simulations show that the compensated ADC has similar performance as the noncompensated ADC operating with GBW=10*fs when subject to the different nonidealities. With an OSR=64 it stays within the accuracy specification for GBWs >= 0.05*fs This is however only valid if actual GBW stays within +-40% of the GBW compensated for. For larger deviations, especially lower GBW values, the SNDR drops rapidly. It is also shown that the internal signal swing in the ADC is reduced for low GBW values. This may limit the practical achievable SNDR when subject to circuit noise. If these potential drawbacks are circumvented, the compensation technique could lead to a further decrease of the power consumption in continuous-time delta-sigma ADCs.

A 64-modulus prescaler operating at 5.8 GHz has been designed in a 0.18 μm CMOS process. The prescaler uses a four-phase high-speed ÷4 circuit at the input, composed of two identical cascaded ÷2 circuits implemented in pseudo-NMOS. The high-speed divider is followed by a two-bits phase switching stage, which together with the input divider forms a ÷4/5/6/7 circuit. The phase switching stage is mostly implemented in complementary CMOS. After this follows four identical ÷2/3 cells with local feedback, also implemented in complementary CMOS. Other architectural approaches are also described and tried out. An architecture based solely the ÷2/3 cells with local feedback is presented. The ÷2/3 cells were implemented and simulated, and worked up to 2.3 GHz. An alternative high-speed divider based on an inverter ring interrupted by transmission gates is also described. Simulations showed that a divider using pseudo-NMOS inverters and CMOS transmission gates operated well and gave out four signals evenly spaced in phase at a input frequency of 4.8 GHz.

Software defined radio (SDR) is an emerging trend of radio technology. The idea is basically to move software as close to the antenna of a radio system as possible, to improve flexibility, adaptability and time-to-market. This thesis covers the description of a DSP architecture especially optimized for modulation / demodulation algorithms of low-complexity, low-power radio standards. The DSP allows software processing of these algorithms, making SDR possible. To make the DSP competitive to traditional ASIC modems, tough constraints are given for area and power consumption. Estimates done to indicate the power consumption, area and computational power of the DSP, shows that a software implementation of the studied physical layer should be possible within the given constraints.

This thesis is divided into two parts, the design of a practical first order open loop sigma-delta modu- lator using discrete components, and simulation of a third order OLSD ADC to investigate the consequences of circuit imperfections - and determining circuit requirements if the ADC should be used in a GSM system. The practical modulator is designed as a first order OLSD ADC, with standard discrete components such as operational amplifiers and switches, and a microcontroller with a built in ADC. The practical circuit uses surface mount capacitors with a tolerance of 20%, resulting in poor matching and inaccurate behavior of the modulo integrator. Despite the poor matching, the OLSD ADC shows a distinct noise shaping, with a slope of about 20dB per decade. The quantization noise is not the dominating noise source in the circuit, and the quantizer resolution must to be set to four bits or less to achieve any improvement in performance over the standard ADC. The third order modulator is modeled and simulated at a behavior level using VHDL-AMS. The ideal circuit confirms the results from the preliminary project [12], where the quantizer resolution had to be equal to or larger than the modulator order to obtain proper noise shaping. The simulations shows that the ideal third order modulator with a four bit quantizer can achieve a SNR of 88:51dB, and an ENOB of 13:78bits within a 200kHz band. The third order modulator is simulated with circuit imperfections to determine the effect of these when there is no feedback present. Introducing finite gain in the integrators results in harmonic distortion at the output. This harmonic distortion is a result of leakage of the internal reset signal in the integrators. By setting the gain in all three integrators to 2OSR = 42dB, the SNR of the third order modulator sinks to 71:74dB. The gain in the ¯rst integrator is increased to 60dB, and the SNR raises to 84:52dB. The first integrator is the most crucial to the performance of the modulator, as is the case for conventional sigma-delta ADCs. The circuit is also simulated with capacitance mismatch and comparator o®set in the modulo integrator. These two imperfections results in the same error - the output voltage from the integrator di®ers from the ideal case. Simulations show that the total voltage error should be significantly less than 0.5VLSB to obtain the noise shaping. If the integrator output error is too large, the noise shaping will totally disappear. In general, it has been proved that the OLSD modulator with modulo integrators works as intended, the quantization noise is shaped like in conventional sigma-delta modulators. The modulator is very sensitive to capacitor mismatch and parasitics. The e®ect of these capacitor imperfections will increase as the quantizer resolution increase, because the error will cover more units of VLSB. It is important to minimize these capacitor effects, as increased quantizer resolution will allow a greater input signal swing.

This master thesis presents the design of a high IIP2 direct-conversion receiver front-end, consisting of a LNA and I- and Q-channel mixers. The front-end is implemented in a 0.18 μm technology with 1.8V supply voltage. Problems that are especially severe for direct-conversion receivers are presented; 1/f-noise, DC offset, and second-order nonlinearity, with particular attention to the latter. Methods to improve the IIP2 are presented and explored in the design of the front-end. The complete front-end has -19.7 dBm IIP3, 4 dB noise figure, and consume 7.4mA of current from a 1.8V supply. Through mixer load tuning an IIP2 of more than +48 dBm is achieved for the front-end.

Two different processors from two FPGA vendors and an OpenCore-processor have been investigated. For this work two different boards were used, the first was the Cyclone II FPGA Altera Board, in which the Nios II Altera microprocessor and the free processor Leon2 were tested. The second board was a SUZAKU-S board, in which the Microblaze Xilinx microprocessor and the free processor Leon2 were tested. We performed two different benchmarks in these boards, the Dhrystone and the Whetstone, to compare the different velocities between the free and not free processors. Also the documentation and ease of use of the processors is considered.

The Lithium-ion battery is today used by close to every portable battery powered device, and this marked is constantly increasing because not only are the products the consumer have had for years getting more and more sophisticated, so he or she often “has” to replace yesterdays model with tomorrows. But as many products are furnished with new functions they use more power, hence their battery life is shortened. Because the Lithium-ion battery is so chemically advanced, it requires a sophisticated management system if it is to be fully utilized by the product. In this report, the parameters of the Lithium-ion battery which are the reason for this strict management are explained. The explanation does not look into the underlying chemistry for them because that is beyond the scope of this report. But sources for further reading on the subject are included. Different solutions for battery management are discussed and a Voltage-to-Frequency (VFC) converter is implemented in VHDL-AMS and simulated in ADVance-MS from Mentor[2]. The sources of error in the design are identified but dealt with in this report. This is not necessary before implementation in a CMOS-process has been shown possible. Simulations without component deviations are good, but once they are introduced, the converter shows that it is too sensitive for them. This can be solved utilizing digital error correction and calibration. After the ideal simulations are performed, transistor level simulations for the circuit are performed. Different solutions and requirements for the various components in the Voltage-to-Frequency converter are looked into with respect to the results found while simulating the ideal circuit. It was found that the comparator should have hysteresis to avoid unwanted chattering in its output signal. The architecture was chosen and the comparator was simulated. It was found that this architecture provided some offset-voltage, but this can easily be compensated by subtracting the offset from its reference voltage. Digital calibration can also here be utilized, but this is not looked into. Two high-gain op-amp architectures are looked into and simulated in this report, it was found that the two-stage used slightly more power than the two-stage op-amp with cascode-output, but they both provided approximately the same gain, even though the two-stage op-amp with cascode-output theoretically should provide about 100 times more gain. From this it is concluded that this architecture has a gain-limit independent of architecture used around 56dB. It is concluded that the Voltage-to-Frequency-architecture looked into is not suitable for implementation in this CMOS-process and that another architecture must be found if a Voltage-to-Frequency converter shall be made for the architecture.

This Master’s thesis documents a new test method for detection of small delay faults in FPGA routing network. The main purpose of the test is accurate detection of faults in all parts of the network. The second aim is minimizing test application time. The work of the thesis consisted of four parts. First, a literature study was performed to get background knowledge of FPGA architecture and basics of testing. Second, detection accuracy was defined and measured in SPICE for test paths with different number of fan-out. Third, test configurations were developed. And finally, detection accuracies for the proposed test method were calculated. The SPICE measurements were performed on an interconnect model of FPGA. They revealed that detection accuracy of defects tested by branches of a test path is less than detection accuracy of defects tested by stems of a test path. In addition, it was observed that detection accuracy is best in the beginning of a test path. In the proposed test method detection accuracy is improved by testing all segments outside switch matrices by test path stems, and applying test patterns to all bidirectional segments in both directions. A comparison to two previous test methods showed that the proposed test method is more accurate while keeping the same number of test configurations. The detection accuracy can be improved further by allowing more test configurations.