In order to inject solar power to the utility grid, among various types of inverters, Grid Connected Transformerless Solar Inverters (GCTSI) are mostly preferred for residential or commercial applications. This preference is because of the high energy efficiency and low cost due to the absence of a line frequency or a high frequency transformer. Peak value of the efficiency characteristics of GCTSIs can reach 98%, which are selected topology, component optimization, switching strategy and operating condition dependent. In spite of the attractive energy efficiency characteristics of GCTSIs, due to the lack of galvanic isolation, these inverters are vulnerable to leakage currents, which are prohibitive for the safety and the maintenance reasons. The purpose of this research is to analyze GCTSIs in terms of their leakage current and energy efficiency characteristics. In the research, the leakage current mechanisms of GCTSIs are identified and grid connected solar inverters are classified in terms of their leakage current characteristics including the GCTSIs. In addition to the existing ones, several novel topologies are proposed enriching the family of GCTSIs. The leakage current and the inductor current ripple performances of GCTSI topologies are analyzed and evaluated by detailed simulations for 3 kVA and 10 kVA single-phase systems. In addition, the energy efficiency characteristics of GCTSIs are investigated in these power levels by making use of Calculated Average Power Per Switching Cycle (CAPPSC) method. The efficiency studies with CAPPSC method provide design guidelines and comparison of the GCTSI topologies in terms of their energy efficiency characteristics.

<p>Semiconductor lasers based on gallium arsenide and relatedmaterials are widely used in applications such as opticalcommunication systems, sensing, compact disc players, distancemeasurement, etc. The performance of these lasers can beimproved using a buried heterostructure offering lateralcarrier and optical confinement. In particular, if theconfinement (burying) layer is implemented by epitaxialregrowth of an appropriate aluminium-free semi-insulating (SI)material, passivation of etched surfaces, reduced tendency tooxidation, low capacitance and integration feasibility areadditional advantages.</p><p>The major impediment in the fabrication of GaAs/AlGaAsburied-heterostructure lasers is the spontaneous oxidation ofaluminium on the etched walls of the structure. Al-oxide actsas a mask and makes the regrowth process extremely challenging.In this work, a HCl gas-based<i>in-situ</i>cleaning technique is employed successfully toremove Al-oxide prior to regrowth of SI-GaInP:Fe and SI-GaAs:Fearound Al-containing laser mesas by Hydride Vapour PhaseEpitaxy. Excellent regrowth interfaces, without voids, areobtained, even around AlAs layers. Consequences of usinginadequate cleaning treatments are also presented. Regrowthmorphology aspects are discussed in terms of different growthmechanisms.</p><p>Time-resolved photoluminescence characterisation indicates auniform Fe trap distribution throughout the regrown GaInP:Fe.Scanning capacitance microscopy measurements demonstrate thesemi-insulating nature of the regrown GaInP:Fe layer. Thepresence of EL2 defects in regrown GaAs:Fe makes more difficultthe interpretation of the characterisation results in the nearvicinity of the laser mesa.</p><p>GaAs/AlGaAs buried-heterostructure lasers, both in-planelasers and vertical-cavity surface-emitting lasers, withGaInP:Fe as burying layer are demonstrated for the first time.The lasers exhibit good performance demonstrating thatSI-GaInP:Fe is an appropriate material to be used for thispurpose and the suitability of our cleaning and regrowth methodfor the fabrication of this type of semiconductor lasers.Device characterisation indicates negligible leakage currentalong the etched mesa sidewalls confirming a smooth regrowthinterface. Nevertheless, experimental and simulation resultsreveal that a significant part of the injected current is lostas leakage through the burying material. This is attributed todouble carrier injection into the SI-GaInP:Fe layer.Simulations also predict that the function of GaInP:Fe ascurrent blocking layer should be markedly improved in the caseof GaAs-based longer wavelength lasers.</p><p><b>Keywords:</b>semiconductor lasers, in-plane lasers, VCSELs,GaAs, GaInP, semi-insulating materials, hydride vapour phaseepitaxy, regrowth, buried heterostructure, leakage current,simulation.</p>

Supercapacitors are well known for their improvised power density compared to batteries. Ongoing research is mainly focused on improving the energy density of supercapacitors by using different electrode material nanocomposites. The recent research has revealed that graphene (G)-polyaniline (PANI) nanocomposite could be a promising material for supercapacitor applications. The supercapacitor is also associated with self-leakage current regardless of any electrode material. The main objectives of the project are to: (i) synthesize highly fabricate supercapacitor based of G-PANI electrode; (ii) improve the energy density of supercapacitor by applying ultrathin monolayer/monolayers film electrode surface. It is crucial to either improve or retain the effective capacitance of the dielectric film. The dielectric material chosen is polyvinylidene fluoride (PVDF) due to its dielectric constant and electrochemical properties. Langmuir-Schaefer (LS) technique is used to deposit the PVDF film onto the substrate. The optical properties of electrode materials were measured by UV-vis spectrophotometer. The surface morphology of the fabricated electrode material has been investigated using scanning electron microscopic (SEM) and atomic force microscopic (AFM) studies. The supercapacitor with and without dielectric layer have been studied using cyclic voltammetry, charging and discharging, and electrochemical impedance techniques, respectively. The specific capacitance has been found to increase by application of one monolayer of PVDF film of G-PANI electrode. However, the LS film of PVDF does not show the minimization of leakage current but revealed an increase in the specific capacitance due to enhancement in surface area associated with the electrode besides PVDF is also an electrochemical active material. The electrochemical investigation of various layers of PVDF on G-PANI in symmetric and asymmetric supercapacitor configuration has been presented in thesis. The future scope of the project could be designing the electrode with various number of layers of dielectric material that could reduce the leakage current, and retaining the specific capacitance of G-PANI nanocomposite electrodes.

The progress of the silicon-based complementary-metal-oxide-semiconductor (CMOS) technology is mainly contributed to the scaling of the individual component. After decades of development, the scaling trend is approaching to its limitation, and there is urgent needs for the innovations of the materials and structures of the MOS devices, in order to postpone the end of the scaling. Atomic layer deposition (ALD) provides precise control of the deposited thin film at the atomic scale, and has wide application not only in the MOS technology, but also in other nanostructures. In this dissertation, I study rapid thermal processing (RTP) treatment of thermally grown SiO2, ALD growth of SiO2, and ALD growth of high-k HfO2 dielectric materials for gate oxides of MOS devices. Using a lateral heating treatment of SiO2, the gate leakage current of SiO2 based MOS capacitors was reduced by 4 order of magnitude, and the underlying mechanism was studied. Ultrathin SiO2 films were grown by ALD, and the electrical properties of the films and the SiO2/Si interface were extensively studied. High quality HfO2 films were grown using ALD on a chemical oxide. The dependence of interfacial quality on the thickness of the chemical oxide was studied. Finally I studied growth of HfO2 on two innovative interfacial layers, an interfacial layer grown by in-situ ALD ozone/water cycle exposure and an interfacial layer of etched thermal and RTP SiO2. The effectiveness of growth of high-quality HfO2 using the two interfacial layers are comparable to that of the chemical oxide. The interfacial properties are studied in details using XPS and ellipsometry.

Nesta dissertação é apresentado o estudo da célula SRAM estática de 6 transistores, com tecnologia CMOS, sendo utilizada em ambiente exposto à radiação. Foi verificado, através de simulação com o Hspice (HSPICE, 2009; KIME, 1998) e com a análise de Monte Carlo, o seu comportamento com relação à dose de ionização total (Total Ionization Dose, TID), a qual altera a tensão de limiar (threshold voltage, Vth) e a corrente de fuga, não sendo utilizada nenhuma técnica de fabricação especial para tolerância à radiação. Na simulação foi observado o comportamento da célula com relação ao tempo de atraso de escrita, à margem de ruído de leitura e ao consumo de energia. As simulações incluem as tecnologias de 130nm e 350nm sendo, portanto, possível comparar os efeitos de radiação citados em ambas, para verificar qual é a mais naturalmente resistente a radiação, verificando se está coerente com resultados divulgados na literatura. Para simular o efeito de dose, altera-se a tensão de limiar (threshold voltage, Vth) com a análise de Monte Carlo e, para a corrente de fuga, adiciona-se uma fonte de corrente entre o dreno e fonte de cada transistor. Os valores de Vth e corrente de fuga foram obtidos nas referências (HAUGERUD, 2005) para a tecnologia 130nm e (LACOE, 1998) para a tecnologia 350 nm. As simulações mostram que o comportamento foi coerente com resultados já conhecidos, em que a tecnologia mais antiga (350nm) tem alterações mais significativas do que a tecnologia mais atual, em relação à TID. / This work presents the study of the static RAM (SRAM) cell with 6 transistor, using CMOS technology, under radiation environment. The electrical behavior of the cell is evaluated using SPICE simulation (HSPICE, 2009; KIME, 1998) and applying Monte Carlo analysis. The effect of total ionization dose is analyzed through the modeling of threshold voltage shifts and leakage currents. The case study processes of this work do not use any special fabrication steps to make the circuit tolerant to radiation. The behavior of the cell related to write propagation time, read noise margin and energy consumption is evaluated through scripts written to support the simulation campaign. The simulations were performed for both 130nm and 350nm technologies, making possible to compare which one is more resistant to radiation. To further explore the dose effect in the case where the radiation does not affect all transistors in exactly the same way, the threshold voltage (Vth) of the transistors is varied randomly in the Monte Carlo analysis. To consider the leakage current, it is added a current source between drain and source of each transistor. The values of Vth and leakage current were obtained in reference (HAUGERUD, 2005) for the 130nm and in reference (LACOE, 1998) for the 350nm technology. The simulations show that the behavior was consistent with results already known, in which the older technology (350nm) is more significant changes then the most current technology, for the TID.

Nesta dissertação é apresentado o estudo da célula SRAM estática de 6 transistores, com tecnologia CMOS, sendo utilizada em ambiente exposto à radiação. Foi verificado, através de simulação com o Hspice (HSPICE, 2009; KIME, 1998) e com a análise de Monte Carlo, o seu comportamento com relação à dose de ionização total (Total Ionization Dose, TID), a qual altera a tensão de limiar (threshold voltage, Vth) e a corrente de fuga, não sendo utilizada nenhuma técnica de fabricação especial para tolerância à radiação. Na simulação foi observado o comportamento da célula com relação ao tempo de atraso de escrita, à margem de ruído de leitura e ao consumo de energia. As simulações incluem as tecnologias de 130nm e 350nm sendo, portanto, possível comparar os efeitos de radiação citados em ambas, para verificar qual é a mais naturalmente resistente a radiação, verificando se está coerente com resultados divulgados na literatura. Para simular o efeito de dose, altera-se a tensão de limiar (threshold voltage, Vth) com a análise de Monte Carlo e, para a corrente de fuga, adiciona-se uma fonte de corrente entre o dreno e fonte de cada transistor. Os valores de Vth e corrente de fuga foram obtidos nas referências (HAUGERUD, 2005) para a tecnologia 130nm e (LACOE, 1998) para a tecnologia 350 nm. As simulações mostram que o comportamento foi coerente com resultados já conhecidos, em que a tecnologia mais antiga (350nm) tem alterações mais significativas do que a tecnologia mais atual, em relação à TID. / This work presents the study of the static RAM (SRAM) cell with 6 transistor, using CMOS technology, under radiation environment. The electrical behavior of the cell is evaluated using SPICE simulation (HSPICE, 2009; KIME, 1998) and applying Monte Carlo analysis. The effect of total ionization dose is analyzed through the modeling of threshold voltage shifts and leakage currents. The case study processes of this work do not use any special fabrication steps to make the circuit tolerant to radiation. The behavior of the cell related to write propagation time, read noise margin and energy consumption is evaluated through scripts written to support the simulation campaign. The simulations were performed for both 130nm and 350nm technologies, making possible to compare which one is more resistant to radiation. To further explore the dose effect in the case where the radiation does not affect all transistors in exactly the same way, the threshold voltage (Vth) of the transistors is varied randomly in the Monte Carlo analysis. To consider the leakage current, it is added a current source between drain and source of each transistor. The values of Vth and leakage current were obtained in reference (HAUGERUD, 2005) for the 130nm and in reference (LACOE, 1998) for the 350nm technology. The simulations show that the behavior was consistent with results already known, in which the older technology (350nm) is more significant changes then the most current technology, for the TID.

Submitted by Lucienne Costa (lucienneferreira@ufcg.edu.br) on 2018-04-24T16:40:39Z No. of bitstreams: 1 BRUNO ALBUQUERQUE DIAS – DISSERTAÇÃO (PPGEE) 2017.pdf: 3277136 bytes, checksum: 1277dbc3bda9c5d90497f95d8bf94878 (MD5) / Made available in DSpace on 2018-04-24T16:40:39Z (GMT). No. of bitstreams: 1 BRUNO ALBUQUERQUE DIAS – DISSERTAÇÃO (PPGEE) 2017.pdf: 3277136 bytes, checksum: 1277dbc3bda9c5d90497f95d8bf94878 (MD5) Previous issue date: 2017-03-17 / CNPq / O acúmulo de poluentes na superfície dos isoladores, que compõem as linhas de transmissão, permite a formação de uma camada de substâncias que, sob incidência de névoa, chuva ou orvalho, produzem soluções condutoras. Na região norte do Brasil, muitos casos de poluição biológica são caracterizados como limo, associação de microalgas e fungos, a resistência dielétrica da superfície do isolador, nestes casos, é reduzida, causando falhas no sistema elétrico. Para investigar o efeito dessa poluição sobre os isoladores, o presente trabalho apresenta um modelo computacional que relaciona o aspecto visual do limo no isolador (intensidade, forma e local) com a sua corrente de fuga obtida por simulação e correlaciona eficiência da simulação com experimentos em laboratório. Os objetos de teste utilizados foram isoladores de disco de vidro, limpos e poluídos com limo. Os isoladores contaminados foram retirados da subestação de Guamá, Pará, Brasil e os experimentos realizados no Laboratório de Alta Tensão da Universidade Federal de Campina Grande, na Paraíba. As simulações computacionais utilizam o Método dos Elementos Finitos e, assim como as medições laboratoriais, foram realizadas para diferentes condições de umidade, uma vez que essa variável tem influência significativa na condutividade do limo. A simulação se mostrou eficiente e os resultados apresentados mostram que é possível estimar a corrente de fuga desse tipo de isolador sob diferentes condições de umidade e diferentes níveis de poluição. / The accumulation of pollutants on surface of insulators allows the formation of a layer of substances that, with mist, rain or dew, produces conductive solutions. The surface dielectric strength, in these cases, is reduced, causing failures in electrical system. In the northern region of Brazil, many cases of biological pollution are characterized as slimes, association of microalgae and fungi. To investigate the effect of this pollution on the insulators, the present work presents a computational model that relates the visual aspect of slime in the insulator (intensity, shape and location) with its leakage current obtained by simulation and correlates efficiency of the simulation with laboratory experiments. Test objects used were glass disk insulators, cleaned and polluted with slime. The contaminated insulators were removed from the Guamá Substation, Pará, Brazil and the tests performed at the High Voltage Laboratory of Federal University of Campina Grande in Paraíba, Brazil. Computational simulations using Finite Element Method and, as well as the laboratory measurements, were performed for different humidity conditions since this variable has a significant influence on slime conductivity. The simulation proved to be efficient and the presented results show that it is possible to estimate leakage current of this type of insulator under different humidity conditions and different levels of pollution.

Nesta dissertação é apresentado o estudo da célula SRAM estática de 6 transistores, com tecnologia CMOS, sendo utilizada em ambiente exposto à radiação. Foi verificado, através de simulação com o Hspice (HSPICE, 2009; KIME, 1998) e com a análise de Monte Carlo, o seu comportamento com relação à dose de ionização total (Total Ionization Dose, TID), a qual altera a tensão de limiar (threshold voltage, Vth) e a corrente de fuga, não sendo utilizada nenhuma técnica de fabricação especial para tolerância à radiação. Na simulação foi observado o comportamento da célula com relação ao tempo de atraso de escrita, à margem de ruído de leitura e ao consumo de energia. As simulações incluem as tecnologias de 130nm e 350nm sendo, portanto, possível comparar os efeitos de radiação citados em ambas, para verificar qual é a mais naturalmente resistente a radiação, verificando se está coerente com resultados divulgados na literatura. Para simular o efeito de dose, altera-se a tensão de limiar (threshold voltage, Vth) com a análise de Monte Carlo e, para a corrente de fuga, adiciona-se uma fonte de corrente entre o dreno e fonte de cada transistor. Os valores de Vth e corrente de fuga foram obtidos nas referências (HAUGERUD, 2005) para a tecnologia 130nm e (LACOE, 1998) para a tecnologia 350 nm. As simulações mostram que o comportamento foi coerente com resultados já conhecidos, em que a tecnologia mais antiga (350nm) tem alterações mais significativas do que a tecnologia mais atual, em relação à TID. / This work presents the study of the static RAM (SRAM) cell with 6 transistor, using CMOS technology, under radiation environment. The electrical behavior of the cell is evaluated using SPICE simulation (HSPICE, 2009; KIME, 1998) and applying Monte Carlo analysis. The effect of total ionization dose is analyzed through the modeling of threshold voltage shifts and leakage currents. The case study processes of this work do not use any special fabrication steps to make the circuit tolerant to radiation. The behavior of the cell related to write propagation time, read noise margin and energy consumption is evaluated through scripts written to support the simulation campaign. The simulations were performed for both 130nm and 350nm technologies, making possible to compare which one is more resistant to radiation. To further explore the dose effect in the case where the radiation does not affect all transistors in exactly the same way, the threshold voltage (Vth) of the transistors is varied randomly in the Monte Carlo analysis. To consider the leakage current, it is added a current source between drain and source of each transistor. The values of Vth and leakage current were obtained in reference (HAUGERUD, 2005) for the 130nm and in reference (LACOE, 1998) for the 350nm technology. The simulations show that the behavior was consistent with results already known, in which the older technology (350nm) is more significant changes then the most current technology, for the TID.

Les besoins de la microélectronique pour les condensateurs de type DRAM sont résumés dans la feuille de route ITRS (International Technology Roadmap for Semiconductors). Pour descendre en dessous du noeud technologique 22 nm, des performances électriques telles qu'une épaisseur d'oxyde équivalent (EOT) < 0.5 nm et un niveau de courant de fuite < 1.10-7 A/cm² à 0.8 V sont nécessaires. Ces performances sont difficiles à atteindre si l'on considère des oxydes standards largement utilisés tels que le SiO2, le Si3N4 ou l'Al2O3. Le dioxyde de Titane constitue un matériau diélectrique de choix pour ce type d'application si l'on considère sa forte constante diélectrique, la plus haute des oxydes binaires. Selon les conditions de croissance de la couche de TiO2, celle-ci peut se présenter sous forme amorphe ou posséder une structure cristalline appelé phase anatase ou phase rutile. Cette dernière présente une très forte constante diélectrique (90 à 170 selon l'orientation de la maille cristalline) et en fait un atout indéniable pour le développement de condensateur DRAM. Toutefois, cette phase rutile est aussi à l'origine d'un fort courant de fuite mesuré à partir des structures Métal - Isolant - Métal (MIM) associées. De ce fait, il est primordial de savoir contrôler ces courants de fuite tout en gardant la forte valeur de constante diélectrique de la phase rutile. Dans ce travail, nous proposons de travailler sur la croissance des couches minces de TiO2 intégrées dans des structures MIM et déposées sur des substrats différents tels que des électrodes de RuO2/Ru ou de Pt. La technique de dépôt employée pour les couches minces de TiO2 est la technique ALD pour son contrôle très précis de l'épaisseur déposée et sa souplesse d'utilisation pour ce type d'applications. Les propriétés physico-chimiques des couches de TiO2 et l'influence du substrat sur ces propriétés sont analysées. Des compositions différentes de diélectriques sont élaborées au moyen de la technique de dépôt par ALD et notamment des couches minces de TiO2 dopés à l'aluminium. Les propriétés électriques de ces couches sont étudiées afin de déterminer les performances électriques des structures MIM associées en termes de courant de fuite et de densité capacitive. / The requirements for future dynamic random access memory (DRAM) capacitors are summarized in the International Technology Roadmap for Semiconductors. For sub-22 nm node, performances like equivalent oxide thickness (EOT) < 0.5 nm and leakage current density < 1.10-7 A/cm² at 0.8 V are required but are difficult to meet. Titanium dioxide (TiO2) is an attractive dielectric material for such application regarding its high dielectric constant (k). Depending on its growth conditions, TiO2 can be prepared in amorphous, anatase or rutile phase. From the structural point of view, it is generally preferred that TiO2 remains amorphous throughout a complete technological process to minimize leakage transport along grain boundaries. However, the rutile phase exhibits very high dielectric constant ranging from 90 to 170, depending on the lattice orientation. Due to this high dielectric constant, TiO2 rutile phase is considered as a promising material for capacitors in future generations of Dynamic Random Access Memories (DRAMs). A key issue is how to control the high leakage current of rutile phase while keeping the highest dielectric constant in order to get the best electrical performances. In this work, we investigate the growth of high dielectric constant rutile TiO2 films in Metal - Insulator - Metal (MIM) structures deposited on different substrates such as RuO2/Ru or Pt electrodes using ALD (Atomic Layer Deposition). A study of physico-chemical properties of TiO2 layer and influence of bottom electrodes on TiO2's crystalline structure is proposed. Different compositions of dielectrics are processed using flexibility of ALD deposition technique, including Al-doped TiO2 layers and pure TiO2 layers. Electrical properties in terms of leakage current or capacitance density of MIM structures embedding that kind of dielectrics and comparison between these MIM structures in terms of electrical performances is proposed in order to determine the best dielectric film composition to meet the requirements for next generation of DRAM capacitors.

A novel insulating cross-arm (ICA) has been developed for new and existing overhead transmission lines of up to 400 kV. The cross-arm consists of four insulating members, end fittings, field grading devices and a nose connection for the attachment of the conductor. The two main structural elements of the assembly have a unique non-cylindrical geometry which gives them improved mechanical characteristics compared to conventional overhead line insulators. The profile for the compression insulator has been designed. After examining six profile variations, it was determined that the lateral orientation which would give the best performance would be with the flat face of the core facing upwards and tilted by 6o. Using the results obtained from performing flashover tests on a conventional 145 kV insulator, the elevation angle for the compression insulator was set to 6o. The dimensions of the compression insulator were calculated based on the assumption that the ICA would be used to uprate an OHL with L3 towers from 275 kV to 400 kV. The optimal insulator profile was determined to be an alternating profile with three different shed sizes, an arcing distance of 3083 mm and a creepage distance of 12470 mm. Electric field grading devices for the ICA were designed. For the LV end, a grading device resembling a ring which follows the general shape of the cross-section of the insulator was designed. For the HV end, an iterative process yielded two designs. First, the ‘butterfly’ grading device was a unibody piece of cast aluminium for all four ICA members. FEA simulations and tests in the laboratory showed that it could effectively control the electric field at voltages of up to 132 kV. The design was patented and the device was used on six cross-arms installed on a live line in Scotland in August 2013. Second, the ‘M-W’ grading device, was a solution made out of four components for managing the field at voltages of up to 400 kV. The device was designed to be easy to install and service, easy and cheap to manufacture and to have minimal visual impact. The compression insulator and the cross-arm assembly were subjected to a multitude of tests adapted from international standards and the Technical Specifications of National Grid. The performed tests aimed to test the electrical characteristics of the cross-arm and the quality of the materials and manufacturing process of the compression insulator. All of the tests were completed successfully except from the corona extinction test for which the appropriate equipment was not available at the time. Two trials were commissioned to examine how the cross-arm performs in a service-like environment. The snow and ice accretion patterns recorded at the mechanical trial site were used for optimising the profile of the compression insulator. The results after a year of continuous monitoring of leakage current and weather conditions at the live trial site showed that there were humidity and visibility thresholds, above 93% for the former and below 400 m for the latter, which increased the average leakage current by 15% on the tension insulators and by 20% on the compression insulators. It was found that when the longitudinal axis of the cross-arm was perpendicular to the weather the leakage current was higher because more of its surface was exposed. The performance of the novel compression insulators was found to be as good as that of the industry standard tension insulators, reaffirming the potency of the design. Finally, on-site observations showed that the ‘butterfly’ grading device could not effectively manage the electric field on the cross-arm at 400 kV, confirming the results of the FEA simulations and testing.