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Due to the complexity of designing digital systems using VLSI parts, a tool for aiding in system level design specification and verification is needed. Functional level modeling languages and simulators provide that tool. An example of such a tool is the N.2 package of software produced by Endot Inc. and soon to be running on a VAX computer at the University of Central Florida. An overview of the N.2 system is presented in this paper with emphasis on the modeling language of N.2, ISP’. A Small Instruction set Computer (SIC), originally specified in HAPL, is designed with this software using several design methodologies. These range from an instruction level implementation to a microcoded register level implementation. The ISP’ source code is provided for each implementation. Comments on the ability of the N.2 software to model systems at various levels of design abstraction are made. A comparison of the functional modeling language of N.2, ISP’ to other functional level design languages is made. Finally, some areas that warrant further investigation are presented.

There are basically three methods of designing Very Large Scale Integrated (VLSI) circuits; Gate Array, Standard Cell, and Full Custom. The objective of this research is to design a VLSI circuit using the Standard Cell approach. A prime requisite for a successful design of these circuits is an integrated Computer Aided Design (CAD) system. The chip design requirements for an integrated CAD system are developed and their interrelationships are presented. As VLSI circuits grow in complexity, the problem of how to test them becomes more difficult. Two methods for testing are defined: 1. Insertion within the system of which the chip is a part, and use of standard system test techniques. 2. Self-test circuitry built into the chip. These testing techniques were used in the VLSI circuit in this report.

Very Large Scale Integration (VLSI) deals with systems complexity rather than transistor size or circuit performance. VLSI design methodology is supported by Computer Aided Design (CAD) and Design Automation (DA) tools, which help VLSI designers to implement more complex and guaranteed designs. The increasing growth in VLSI complexity dictates a hierarchical design approach and the need for hardware DA tools. This paper discusses the generalized Design Procedure for CAD circuit design; the commercial CADs offered by CALMA and the Caesar System, supported by the Berkeley design tools. A complete design of a Content Addressable Memory (CAM) cell, using the Caesar system, supported by Berkeley CAD tools, is illustrated.

Solving the linear quadratic regulator (LQR) problem for partial differential equations (PDEs) leads to many computational challenges. The primary challenge comes from the fact that discretization methods for PDEs typically lead to very large systems of differential or differential algebraic equations. These systems are used to form algebraic Riccati equations involving high rank matrices. Although we restrict our attention to control problems with small numbers of control inputs, we allow for potentially high order control outputs. Problems with this structure appear in a number of practical applications yet no suitable algorithm exists. We propose and analyze solution strategies based on applying model order reduction methods to Chandrasekhar equations, Lyapunov/Sylvester equations, or combinations of these equations. Our numerical examples illustrate improvements in computational time up to several orders of magnitude over standard tools (when these tools can be used). We also present examples that cannot be solved using existing methods. These cases are motivated by flow control problems that are solved by computing feedback controllers for the linearized system. / Ph. D.