A modified CVD reactor was designed with a deposition chamber capable of accommodating 8" wafers, with the capacity to remotely pyrolyze two different precursors. The design was based on a previous working reactor, with the most notable improvements being a showerhead design for more even delivery of gaseous precursor and a separate heating control of the substrate holder and deposition chamber walls. The performance of the reactor was analyzed by testing the pressure gradients within and the thickness uniformity of films deposited on 8" wafers. The reactor exhibited a linear pressure gradient within, and the thickness uniformity was excellent, with a slight increase in thickness towards inlet of the showerhead. The thickness difference between the maximum and minimum thickness on an 8" wafer was 14%. Films of polyparaxylylene (PPXN), polychloroparaxylylene (PPXC), SiO₂, and PPXC/SiO₂ were deposited, with deposition rates and indices of refraction comparable to those obtained on the old reactor design. A full factorial study was performed to determine the effect of the substrate temperature, the sublimation temperature, and the pyrolysis temperature on the deposition rates of PPXC. It was determined that the substrate temperature has the greatest effect, with about 50% contribution, and deposition rates increased with decreasing substrate temperature. The sublimation temperature contributed 25%, with increasing sublimation rates leading to higher deposition rates. The pyrolysis contributes very little, with about 2%, and the variance ratio did not fall within a 90% confidence level. A low dielectric constant polymer, poly(tetrafluoro-p-xylylene) (VT-4), was synthesized by chemical vapor deposition from 4,5,7,8,12,13,15,16-octafluoro-[2.2]-paracyclophane (DVT-4). The main motivation was to find a cheaper alternative to poly( alpha, alpha , alpha ', alpha '-tetrafluoro-p-xylylene) (AF-4) with similar properties. The dielectric constant of VT-4 was measured as 2.42 at 1 MHz, and the in-plane and out-of-plane indices of refraction were 1.61 and 1.47 at 630 nm. The large negative birefringence suggests a low out-of-plane dielectric constant, which is desired for interlayer dielectrics. The VT-4 polymer was found to be stable at 460 °C by thermogravimetric analysis (TGA). Polymer/Siloxane nanocomposites were studied as an alternate path to a polymer/silica composite. This study showed that incorporation of a four-ringed liquid siloxane precursor into the parylene PPXC is not feasible. A solid precursor cube-like molecule, vinyl-T8, was incorporated with ease. Pyrolysis of vinyl-T8 at different temperatures revealed complex behavior, with the formation of polymerized vinyl-T8 (through free radical addition at the vinyl groups) as well as silica-like structures forming above 500 °C as a result of the breaking up of the cage structure of vinyl-T8. Codepositions of PPXC and vinyl-T8 were then examined as a possible path towards a polymer/silica nanocomposite. At deposition temperatures below 5 °C, precipitation of excess vinyl-T8 into cubic micron-sized crystals occurred. As this was undesirable, studies were continued at higher deposition temperatures. A Taguchi orthogonal array was set up to study the effect of the sublimation temperatures of the two precursors as well as the pyrolysis temperature and the substrate temperature on the deposition rate, the index of refraction and the weight loss after a 500 °C anneal. The deposition rate depended mostly on the sublimation temperature of the PPXC and the substrate temperature. The lowest index of refraction (and thus the lowest dielectric constant) was obtained with the lowest sublimation temperatures of 134 °C for PPXC and 195 °C for vinyl-T8 and a pyrolysis temperature of 200 °C. Each of the factors was found to have an effect on the index of refraction, with the sublimation temperature of vinyl-T8 having the most influence. The films degraded at 500 °C, indicating that post-deposition annealing of the films did not lead to a conversion of the vinyl-T8 to a SiO₂-like structure (which would be stable at that temperature). X-ray diffraction spectra of the films revealed peaks which were not present for any of the vinyl-T8 films or characteristic of PPXC. Therefore, some type of interaction between the two components occurred and affected the morphology, most likely the formation of a block copolymer. Thus, though polymer/silica films were not attained, the resulting composites had comparable properties with higher deposition rates and a cleaner process. / Master of Science

In an effort to lower interconnect time delays and power dissipation in highly integrated logic and memory nanoelectronic products, numerous changes in the materials and processes utilized to fabricate the interconnect have been made in the past decade. Chief among these changes has been the replacement of aluminum (Al) by copper (Cu) as the interconnect metal and the replacement of silicon dioxide (SiO2) by so called low dielectric constant (low-k) materials as the insulating interlayer dielectric (ILD). Cu/low-k structure significantly decreases the RC delay compared with the traditional interconnect (Al/SiO₂). Therefore, the implementation of low-k dielectric in Cu interconnect structures has become one of the key subjects in the microelectronics industry. Incorporation of pores into the existing low-k dielectric is a favorable approach to achieve ultra low-k ILD materials. To bring memory and logic closer together is an effective approach to remove the latency constraints in metal interconnects. The resistive random access memories (RRAM) technology can be integrated into a complementary metal-oxide-semiconductor (CMOS) metal interconnect structure using standard processes employed in back-end-of-line (BEOL) interconnect fabrication. Based on this premise, the study of this thesis aims at assessing a possible co-integration of resistive switching (RS) cells with current BEOL technology. In particular, the issue is whether RS can be realized with porous dielectrics, and if so, what is the electrical characterization of porous low-k/Cu interconnect-RS devices with varying percentages of porosity, and the diffusive and drift transport mechanism of Cu across the porous dielectric under high electric fields. This work addresses following three areas: 1. Suitability of porous dielectrics for resistive switching memory cells. The porous dielectrics of various porosity levels have been supplied for this work by Intel Inc. In course of the study, it has been found that Cu diffusion and Cu+ ion drift in porous materials can be significantly different from the corresponding properties in non-porous materials with the same material matrix. 2. Suitability of ruthenium as an inert electrode in resistive switching memory cells. Current state-of-the-art thin Cobalt (Co)/Tantalum Nitride (TaN) bilayer liner with physical vapor deposited (PVD) Cu-seed layer has been implemented for BEOL Cu/low-k interconnects. TaN is used for the barrier and Co is used to form the liner as well as promoting continuity for the Cu seed. Also, the feasibility of depositing thin CVD ruthenium (Ru) liners in BEOL metallization schemes has been evaluated. For this study, Ru is used as a liner instead of Ta or Co in BEOL interconnects to demonstrate whether it can be a potential candidate for replacing PVD-based TaN/Ta(Co)/Cu low-k technology. In this context, it is of interest to investigate how Ru would perform in well-characterized RS cell, like Cu/TaOx/Ru, given the fact that Cu/TaOx/Pt device have been proven to be good CBRAM device due to its excellent unipolar and bipolar switching characteristics, device performance, retention, reliability. If Cu/TaOx/Ru device displays satisfactory resistive switching behavior, Cu/porous low-k dielectric/Ru structure could be an excellent candidate as resistive switching memory above the logic circuits in the CMOS back-end. 3. Potential of so-called covalent dielectric materials for BEOL deployment and possibly as dielectric layer in the resistive switching cells. The BEOL reliability is tied to time dependent failure that occurs inside dielectric between metal lines. Assessing the suitability of covalent dielectrics for back-end metallization is therefore an interesting topic. TDDB measurements have been performed on pure covalent materials, low-k dielectric MIM and MI-semiconductor (MIS) devices supplied by Intel Inc. / Master of Science / While the scaling of conventional memories based on floating gate MOSFETs is getting increasingly difficult, novel types of non-volatile memories, such as resistive-switching memories, have recently been of interest to both industry and academia. Resistive switching memory is being considered for next-generation non-volatile memory due to relatively high switching speed, high scalability, low power consumption, good retention and simple structure. Additionally, these twoterminal devices operate by changing resistance from high resistance OFF-state (HRS) to low resistance ON-state (LRS) in response to applied voltage or current due to the formation and rupture of a conductive filament. In particular, Conductive Bridging Random Access Memory (CBRAM), also referred as Programmable Metallization Cell (PMC), is a promising candidate for a resistive memory device due to its highly scalable and low-cost technology. Currently, the interconnect RC scaling methods have reached their limits and there is an urgent need for alternative ways to reduce or remove the latency constraints in CMOS low-k/Cu interconnect. One method is building CBRAM directly into a low-k/Cu interconnects to reduce the latency in connectivity constrained computational devices and the chip’s footprint by stacking memory on top of logic circuits. This is possible since the Cu metal lines and low-k/Cu interconnect already prefigure a potential RS device. This work addresses three areas: Firstly, the suitability of porous dielectrics for resistive switching memory cells. Secondly, the suitability of ruthenium as an inert electrode in resistive switching memory cells. If Ru resistive memory device displays satisfactory resistive switching behavior, Cu/porous low-k dielectric/Ru structure could be an excellent candidate as resistive switching memory above the logic circuits in the CMOS back-end-of-line (BEOL). Thirdly, the potential of so-called covalent dielectric materials for BEOL deployment and possibly as dielectric layer in the resistive switching cells.

An alternative indirect integration regime of porous low-k materials was investigated. Based on a single Damascene structure the intra level dielectric SiO2 or damaged ULK was removed by using HF:H2O solutions to create free standing metal lines. The free spaces between the metal lines were refilled with a spin-on process of a low-k material. The persistence of barrier materials and copper against HF solutions, the gap fill behavior of the used spin on glass on different structure sizes and the main challenges which have to solve in the future are shown in this study.

Chip-package interaction (CPI) has become a critical reliability issue for flip-chip packaging of Cu/low-k chip with organic substrate. The thermo-mechanical deformation and stress develop inside the package during assembly and subsequent reliability tests due to the mismatch of the coefficients of thermal expansion (CTEs) between the chip and the substrate. The thermal residual stress causes many mechanical reliability issues in the solder joints and the underfill layer between die and substrate, such as solder fatigue failure and underfill delamination. Moreover, the thermo-mechanical deformation of the package can be directly coupled into the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The thermo-mechanical reliability risk is further aggravated with the implementation of ultra low-k dielectric for better electrical performance and the mandatory change from Pb-containing solders to Pb-free solders for environmental safety. These CPI-induced reliability issues in flip-chip packaging of Cu/low-k chips are investigated in this dissertation at both chip level and package level using high-resolution Moiré interferometry and Finite Element Analysis (FEA). Firstly, the thermo-mechanical deformation in flip-chip packages is analyzed using high-resolution Moiré interferometry. The effect of underfill properties on package warpage is studied and followed by a strategy study of proper underfill selection to improve solder fatigue life time and reduce the risk of interfacial delamination in underfill and low-k interconnects under CPI. The chip-package interaction is found to maximize at the die attach step during assembly and becomes most detrimental to low-k chip reliability because of the high thermal load generated by the solder reflow process before underfilling. A three-dimensional (3D) multilevel sub-modeling method combined with modified virtual crack closure (MVCC) technique is employed to investigate the CPI-induced interfacial delamination in Cu/low-k interconnects. It is first focused on the effects of dielectrics and solder materials on low-k interconnect reliability and then extended to the scaling effect where the reduction of the interconnect dimension is accompanied with an increased number of metal levels and the implementation of ultralow-k porous dielectrics. Recent studies on CPI-induced crack propagation in the low-k interconnect and the use of crack-stop structures to improve the chip reliability are also discussed. Finally, 3D integration (3DI) with through silicon vias (TSV) has been proposed as the latest solution to increase the device density without down-scaling. The thermo-mechanical reliability issues facing 3DI are analyzed. Three failure modes are proposed and studied. Design optimization of 3D interconnects to reduce the thermal residual stress and the risks of fracture and delamination are discussed. / text

Le collage direct consiste à l’adhésion spontanée dès température ambiante de deux surfaces sans ajout de matière polymère à l’interface de collage. Réalisable sous vide ou à pression atmosphérique, il possède l’avantage de permettre l’empilement de matériaux monocristallins sur des matériaux amorphes, parfaitement illustrée, par exemple, avec la fabrication de substrats SOI (silicium sur isolant) couramment utilisé de nos jours en microélectronique et/ou en microtechnologie. La course à la performance et/ou pluridisciplinarité des circuits électroniques nécessite la maîtrise de ce procédé pour un plus large panel de matériaux. La compréhension des mécanismes physico-chimique à l’interface de collage devient alors primordiale. L’objectif de cette thèse est d’étudier les mécanismes mis en jeu dans le collage direct hydrophile de couches diélectriques autres que l’oxyde de silicium : l’oxyde d’aluminium, le nitrure de silicium et un ultra-low k.Dans cette étude, des procédés de collage direct hydrophile de films diélectriques déposés sont développés avec différentes préparations de surface. L’évolution mécanique et chimique de l’interface de collage, après différents traitements thermiques, est analysé via différentes techniques de caractérisation comme la mesure anhydre d’énergie de collage, la microscopie acoustique, la réflectivité des rayons X et la spectroscopie infrarouge. Chaque matériau démontre un comportement particulier une fois confiné à l’interface de collage par rapport à son comportement en surface libre. Tout au long de cette thèse, le lien entre collage et surface libre a permis d’établir les mécanismes de collages des différents matériaux étudiés et d’énoncer des recommandations pour obtenir des collages de qualité. / Direct wafer bonding refers to the spontaneous establishment of attractive forces between two surfaces at ambient temperature without any additional polymer material. Available at ambient pressure or under vacuum, this technology is attractive for monocrystal-amorphous stacks, perfectly illustrated by SOI (Silicon On Insulator) substrate elaboration widely used nowadays in microelectronics or microtechnologies. Electronic device performance and multidisciplinarity needs require this technology on many different materials. In this context, a precis understanding of bonding mechanism is paramount. The aim of this work is to study the hydrophilic bonding mechanisms for alumina, nitride silicon and ultra-low k thin films.In this study, hydrophilic bonding of deposited dielectric films prepared by chemical treatment were analyzed as function of post-bonding annealing temperature. Chemical and mechanical bonding interface closure has been analyzed from mechanical and chemical point of view via several characterization techniques: anhydrous bonding energy measurement, acoustic microscopy, X-Ray reflectivity and infrared spectroscopy. Each material demonstrates interesting behaviors embedded at the bonding interface compared to the deposited film free surfaces. Throughout the studies, correlations between bonding and free surface evolution have led to their bonding mecanisms and some recommendations for efficient and high quality bonding elaboration.

Plasma induced damage of ultra low-k (ULK) dielectrics is a common phenomenon in BEOL interconnects. The damage leads to an increase in k-value, which raises the RC delay, leading to increased power consumption and cross talk noise. Therefore, diverse repair and post etch treatments (PET) have been proposed to restore or reduce the ULK damage. However, current repair processes are usually based on non-plasma silylation, which suffers from limited chemistry diffusion into the ULK. Moreover, the conventional PET based on anisotropic plasma results in bottom vs. sidewall inhomogeneities of the structures (e.g. via and trench). To reduce these drawbacks, an organosilane downstream -plasma (DSP) was applied. This new application resulted in an increased resistance to ULK removal by fluorinated wet clean chemistries, preserving the ULK hydrophobicity, keeping its carbon content relatively high. The effective RC measured on 28 nm node patterned wafers treated with a DSP PET remains nevertheless comparable to the process of record (POR).

Integration of dielectrics with increased porosity is required to reduce the capacitance of interconnects. However, the conventional dual damascene integration approach is causing negative effects to these materials avoiding their immediate implementation. A post-CMP curing approach could solve some of these issues. However, materials with porogens being stable at temperatures of the barrier-seed deposition process are not common, hindering this approach. Here, we report on an extended dual-damascene integration approach which permits post-CMP curing.

Die fortwährende Verkleinerung der Strukturbreiten in der Mikroelektronik erfordert es, herkömmliche SiO2 Dielektrika durch Materialien mit kleinerer Dielektrizitätskonstante zu ersetzen. Dafür sind verschiedene „low-k Materialien“ entwickelt worden. Unter diesen sind die Organosilikatgläser, die aus SiO2 Netzwerken mit eingelagerten Methylgruppen bestehen wegen ihrer ausgezeichneten Eigenschaften besonders interessant als Dielektrika zwischen metallischen Leiterbahnen. In dieser Arbeit sind fünf verschiedene dieser „low-k Materialien“ untersucht worden: ein dichtes und vier poröse Materialien, die alle durch plasmagestützte chemische Gasphasenabscheidung hergestellt wurden. Die strukturellen, chemischen und dielektrischen Eigenschaften der Materialien wurden mit Hilfe der analytischen Durchstrahlungselektronenmikroskopie unter Verwendung eines abbildenden GATAN-Energiespektrometers untersucht. Die Bestimmung der radialen Verteilungsfunktion (RDF) zur Charakterisierung der atomaren Nahordnung ermöglicht uns die Ermittlung mittlerer Bindungslängen und – winkel sowie der mikroskopischen Dichte des Materials. Gegenüber SiO2 wurden in den untersuchten „low-k Materialien“ stark veränderte mittlere Si-O, O-O und Si-Si Bindungslängen gefunden. Dieses wirkt sich natürlich auch auf die mittleren Si-O-Si bzw. O-Si-O Bindungswinkel aus, und wie erwartet war auch die mikroskopische Dichte der „low-k Materialien“ kleiner als die Dichte des SiO2. Elektronen Energieverlustspektroskopie (EELS) und Photoelektronenspektroskopie (XPS) wurden zur Charakterisierung der chemischen Umgebung der Atome in den „low-k Materialien“ herangezogen. Die Energien von Ionisationskanten und die Bindungsenergien der Silizium-2p und Sauerstoff-1s Elektronen waren in den „low-k Materialien“ größer als im SiO2. Die Kohlenstoffatome kamen in den „low-k Materialien“ sowohl sp2 als auch sp3 hybridisiert vor. sp2-Hybridisierung liegt vor, wenn Bindungen wie Si=CH2 und C=C im Netzwerk vorkommen, während sp3 Hybridisierung z.B. dann vorkommt, wenn freie Si-Bindungen durch –CH3 Gruppen abgesättigt werden. Die Anteile an sp2- bzw. sp3-hybridisierten Kohlenstoffatome wurden aus der Feinstruktur der K-Energieverlustkanten des Kohlenstoffs abgeschätzt. Das ergab, daß die meisten Kohlenstoffatome in den „low-k Materialien“ sp2-hybridisiert sind. Die dielektrischen Eigenschaften wurden durch Kramers-Kronig-Transformation einer Energieverlustfunktion ermittelt, die aus dem Niedrigverlust-EELS-Spektrum im Bereich der Plasmonenanregungen gewonnen wurde. Die Bandlücke des SiO2 beträgt ungefähr 9 eV während dichte „low-k Materialien“ aufgrund der Unregelmäßigkeiten in ihrem SiO2-Netzwerk zusätzliche Zustandsdichten innerhalb der Bandlücke aufweisen. Die Erzeugung von Poren im „low-k Material“ vermindert offenbar die Zustandsdichte im Bereich der Bandlücke und erweitert diese im Vergleich zum SiO2. Eine Modellrechnung mit der Dichtefunktionaltheorie für ein Strukturmodell, das den „low-k Materialien“ nahe kommt, ist zum Vergleich mit der experimentell gefundenen kombinierten Zustandsdichte herangezogen worden und zeigt eine gute Übereinstimmung. Die im Standard-Herstellungsprozeß vorkommenden Verfahren des Plasmaätzens und der Plasmaveraschung können die Struktur des „low-k Materials“ z.B. an den Seitenwänden von Ätzgräben verändern. Die gestörten Bereiche wurden mit der energiegefilterten Elektronenmikroskopie untersucht. Dabei wurde gefunden, daß sich die Strukturveränderungen der Seitenwände bis zu einer Tiefe in der Größenordnung von ungefähr 10 Nanometern erstrecken. Diese Bereiche sind verarmt an Kohlenstoff und ähneln folglich mehr einem SiO2-Dielektrikum. Die Kohlenstoffverarmung erstreckt sich in die „low-k Schicht“ in Form eines gaussartigen Profils mit maximaler Kohlenstoffkonzentration in der Mitte der Schicht. Die Sauerstoffkonzentration und die mikroskopische Dichte steigen in der Nähe der Seitenwände.

Since its inception as the Tungsten Workshop in 1984, AMC has served as the leading conference for the interconnect and contact metallization communities, and has remained at the leading edge of the development of tungsten, aluminum, and copper/low-K interconnects. As the semiconductor industry evolves, exciting new challenges in metallization are emerging, particularly in the areas of contacts to advanced devices, local interconnect solutions for highly-scaled devices, advanced memory device metallization, and 3D/packaging technology. While the conference content has evolved, the unique workshop environment of AMC fosters open discussion to create opportunities for cross-pollination between academia and industry. Submissions are covering materials, process, integration and reliability challenges spanning a wide range of topics in metallization for interconnect/contact applications, especially in the areas of: - Contacts to advanced devices (FinFET, Nanowire, III/V, and 2D materials) - Highly-scaled local and global interconnects - Beyond Cu interconnect - Novel metallization schemes and advanced dielectrics - Interconnect and device reliability - Advanced memory (NAND/DRAM, 3D NAND, STT and RRAM) - 3D and packaging (monolithic 3D, TSV, EMI) - Novel and emerging interconnects Executive Committee: Sang Hoon Ahn (Samsung Electronics Co., Ltd.) Paul R. Besser (Lam Research) Robert S. Blewer (Blewer Scientific Consultants, LLC) Daniel Edelstein (IBM) John Ekerdt (The University of Texas at Austin) Greg Herdt (Micron) Chris Hobbs (Sematech) Francesca Iacopi (Griffith University) Chia-Hong Jan (Intel Corporation) Rajiv Joshi (IBM) Heinrich Koerner (Infineon Technologies) Mehul Naik (Applied Materials Inc.) Fabrice Nemouchi (CEA LETI MINATEC) Takayuki Ohba (Tokyo Institute of Technology) Noel Russell (TEL Technology Center, America) Stefan E. Schulz (Chemnitz University of Technology) Yosi Shacham-Diamand (Tel-Aviv University) Roey Shaviv (Applied Materials Inc.) Zsolt Tokei (IMEC)

Avec la miniaturisation des circuits intégrés, le délai de transmission dû aux interconnexions a fortement augmenté. Pour limiter cet effet parasite, le SiO2 intégré en tant qu'isolant entre les lignes métalliques a été remplacé par des matériaux diélectriques à plus faible permittivité diélectrique dits Low-κ. La principale approche pour élaborer ces matériaux est de diminuer la densité en incorporant de la porosité dans des matériaux à base de SiOCH. L'introduction de ces matériaux peu denses a cependant diminué la fiabilité : sous tension, le diélectrique SiOCH poreux est traversé par des courants de fuite et peut claquer, générant des défaillances dans le circuit. La problématique pour l'industriel est de comprendre les mécanismes de dégradation du diélectrique Low-κ afin de déterminer sa durée de vie aux conditions de température et de tension de fonctionnement. Dans ce contexte, les travaux de cette thèse ont consisté à étudier les mécanismes de conduction liés aux courant de fuite afin d'extraire des paramètres quantitatifs représentatifs de l'intégrité électrique du matériau. Nous avons utilisé ces paramètres afin de suivre le vieillissement du matériau soumis à une contrainte électrique. Nous avons également introduit la spectroscopie d'impédance à basse fréquence comme moyen de caractérisation du diélectrique Low-κ. Cet outil nous a permis de caractériser le diélectrique intermétallique de façon non agressive et d'identifier des phénomènes de transport de charges et de diffusion métallique à très basses tensions qui offrent des perspectives pour l'étude de la fiabilité diélectrique des interconnexions. / With the miniaturization of integrated circuits, transmission delay due to interconnects is hardly increased. To minimize this parasitic effect, low-κ dielectric materials are requested to replace SiO2 as inter-metal dielectric between metallic lines. With its low density, porous SiOCH are good candidate for such applications. However, the implementation of these materials decreased reliability: under voltage, leakage currents establish through low-κ dielectric whose breakdown can generate failures in circuits. The problem for manufacturers is to understand the degradation mechanisms of porous SiOCH to determine its lifetime at conditions of nominal temperature and voltage. In this frame, conduction mechanisms of leakage currents have been studied during this thesis to extract quantitative parameters that represent the electrical integrity of the dielectric. We have used these parameters to monitor the electrical aging of the dielectric under electrical stress. We have proposed low-frequency impedance spectroscopy as characterization tool of low-κ. This tool allowed to characterize the intermetal dielectric non-destructively and to identify phenomenon of carriers transport and metallic diffusion at very low voltages that open perspectives for the study of dielectric reliability in interconnects.