Master of Science / Electrical and Computer Engineering / Dwight D. Day / Synchronization is one of the most critical steps in a wireless communication system. With the system having limited energy resources, low power devices and designs are key aspects of the design process. Digital communication and decoding is discussed along with how synchronization is part of communication. The parameters for wireless communication are outlined and how the system can be simplified in order to reduce power consumption for the network is investigated. The background for the Body Area Network Board which was created for the project, Biosensor Networks and Telecommunication Subsystems for Long Duration Missions, EVA Suits, and Robotic Precursor Scout Missions, is discussed along with some synchronization background as well as some previously researched demodulators designed for limited preambles. With limited-length preambles, oversampling is needed to achieve synchronization. This research investigates what minimum oversampling ratio is needed in a simplified system to still achieve packet synchronization and several synchronization words were compared. The parameters for packet synchronization are outlined as well the impulse noise model used for simulation. For the simulation and the test setup, several oversampling ratios and synchronization words are compared using probability of miss detection and probability of false detection. The oversampling ratio of 16 was shown to be a critical point where increasing the oversampling rate above 16 had diminishing returns. In terms of probability of miss detection, the 7-bit Barker sequence along with the start of frame delimiter for IEEE 802.15.4 had better performance compared to the start of frame delimiter for Ethernet and the sequence 01010111.

abstract: This thesis dissertation presents design of portable low power Electrochemical Impedance Spectroscopy (EIS) system which can be used for biomedical applications such as tear diagnosis, blood diagnosis, or any other body-fluid diagnosis. Two design methodologies are explained in this dissertation (a) a discrete component-based portable low-power EIS system and (b) an integrated CMOS-based portable low-power EIS system. Both EIS systems were tested in a laboratory environment and the characterization results are compared. The advantages and disadvantages of the integrated EIS system relative to the discrete component-based EIS system are presented including experimental data. The specifications of both EIS systems are compared with commercially available non-portable EIS workstations. These designed EIS systems are handheld and very low-cost relative to the currently available commercial EIS workstations. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2016

abstract: Today's mobile devices have to support computation-intensive multimedia applications with a limited energy budget. In this dissertation, we present architecture level and algorithm-level techniques that reduce energy consumption of these devices with minimal impact on system quality. First, we present novel techniques to mitigate the effects of SRAM memory failures in JPEG2000 implementations operating in scaled voltages. We investigate error control coding schemes and propose an unequal error protection scheme tailored for JPEG2000 that reduces overhead without affecting the performance. Furthermore, we propose algorithm-specific techniques for error compensation that exploit the fact that in JPEG2000 the discrete wavelet transform outputs have larger values for low frequency subband coefficients and smaller values for high frequency subband coefficients. Next, we present use of voltage overscaling to reduce the data-path power consumption of JPEG codecs. We propose an algorithm-specific technique which exploits the characteristics of the quantized coefficients after zig-zag scan to mitigate errors introduced by aggressive voltage scaling. Third, we investigate the effect of reducing dynamic range for datapath energy reduction. We analyze the effect of truncation error and propose a scheme that estimates the mean value of the truncation error during the pre-computation stage and compensates for this error. Such a scheme is very effective for reducing the noise power in applications that are dominated by additions and multiplications such as FIR filter and transform computation. We also present a novel sum of absolute difference (SAD) scheme that is based on most significant bit truncation. The proposed scheme exploits the fact that most of the absolute difference (AD) calculations result in small values, and most of the large AD values do not contribute to the SAD values of the blocks that are selected. Such a scheme is highly effective in reducing the energy consumption of motion estimation and intra-prediction kernels in video codecs. Finally, we present several hybrid energy-saving techniques based on combination of voltage scaling, computation reduction and dynamic range reduction that further reduce the energy consumption while keeping the performance degradation very low. For instance, a combination of computation reduction and dynamic range reduction for Discrete Cosine Transform shows on average, 33% to 46% reduction in energy consumption while incurring only 0.5dB to 1.5dB loss in PSNR. / Dissertation/Thesis / Ph.D. Electrical Engineering 2012

abstract: The medical industry has benefited greatly by electronic integration resulting in the explosive growth of active medical implants. These devices often treat and monitor chronic health conditions and require very minimal power usage. A key part of these medical implants is an ultra-low power two way wireless communication system. This enables both control of the implant as well as relay of information collected. This research has focused on a high performance receiver for medical implant applications. One commonly quoted specification to compare receivers is energy per bit required. This metric is useful, but incomplete in that it ignores Sensitivity level, bit error rate, and immunity to interferers. In this study exploration of receiver architectures and convergence upon a comprehensive solution is done. This analysis is used to design and build a system for validation. The Direct Conversion Receiver architecture implemented for the MICS standard in 0.18 µm CMOS process consumes approximately 2 mW is competitive with published research. / Dissertation/Thesis / Ph.D. Electrical Engineering 2012

Para manter o desempenho a uma tensão de alimentação reduzida, a tensão de threshold e as dimensões dos transistores têm sido reduzidas por décadas. A miniaturização do transistor para tecnologias sub-100nm resulta em um expressivo incremento nas correntes de fuga, tornando-as parte significativa da potencia total, alcançando em muitos casos 30-50% de toda a potencia dissipada em condições normais de operação. Por estas condições, correntes estáticas em células CMOS representam um importante desafio em tecnologias nanométricas, tornando-se um fator crítico no design de circuitos de baixa potência. Isto significa que dissipação de potência estática deve ser considerada o quanto antes no fluxo de projetos de circuitos integrados. Esta tese revisa os principais mecanismos de fuga e algumas técnicas de redução. Também é apresentado um modelo de estimativa rápida da corrente de subthreshold em células lógicas CMOS série - paralelo. Este método é baseado em associações de condutividade elétrica série – paralelo de transistores. Ao combinar com o modelo de estimativa da corrente de fuga de gate baseada nas condições estáticas dos transistores é possível fornecer uma melhor predição da corrente de fuga total em redes de transistores. O modelo de estimativa anterior é rápido porem seu foco não esta na precisão. Um novo e preciso modelo para corrente de fuga de subthreshold e de gate é também apresentado baseado em modelos analíticos simplificados das correntes de fuga. Ao contrario do modelo anterior que era destinado a redes de transistores serie – paralelo, o novo método avalia as correntes de fuga em rede de transistores complexas. A presença de transistores conduzindo em redes de transistores não conduzindo, ignorados em trabalhos anteriores, é também avaliado no trabalho proposto. O novo modelo de corrente de fuga foi validado através de simulações elétricas, considerando processos CMOS 130nm e 90nm, com boa correlação dos resultados, demonstrando a precisão do modelo. / To maintain performance at reduced power supply voltage, transistor threshold voltages and dimensions have been scaled down for decades. Scaling transistor into the sub-100nm technologies has resulted in a dramatic increase in leakage currents, which have become a significant portion of the total power consumption in scaled technologies, in many case achieving 30-50% of the overall power consumption under nominal operating conditions. For this condition, standby currents in CMOS logic gates represent an important challenge in nanometer technologies, leakage dissipation being a critical factor in low-power design. It means the static power dissipation should be considered as soon as possible in the integrated circuit design flow. This thesis reviews the major leakage current mechanisms and several reduction techniques. It presents the development of a straightforward method for very fast estimation of subthreshold current in CMOS series-parallel logic gates. This estimation method is based on electrical conductivity association of series-parallel transistor arrangements. Combined with a gate oxide leakage model based on transistor bias condition, it is possible to provide a better prediction of total leakage consumption in transistor networks. The previous estimation method is fast but it is not focused on accuracy. A new accurate subthreshold and gate leakage current estimation method is also developed based on simplified analytical leakage currents models. Instead of previous works focused on series-parallel device arrangements, this method evaluates the leakage in general transistor networks. The presence of on-switches in off-networks, ignored by previous works, is also considered in the proposed static current analysis. The new leakage model has been validated through electrical simulations, taking into account a 130nm and 90nm CMOS technology, with good correlation of the results, demonstrating the model accuracy.

Made available in DSpace on 2014-06-12T15:57:04Z (GMT). No. of bitstreams: 2 arquivo3137_1.pdf: 1263423 bytes, checksum: 6193c47086f4fa0833586f510e15f675 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2010 / Atualmente, a redução do consumo de potência é um dos principais desafios no domínio de projeto de circuitos integrados digitais. A evolução da tecnologia de fabricação dos circuitos integrados, chegando a dimensões nanométricas nos dias atuais, torna os problemas relacionados ao consumo de potência ainda mais críticos devido à alta densidade de transistores no chip. Apesar do crescente aumento do consumo de potência estática, a potência dinâmica, dissipada quando o nível lógico do transistor está em transição, ainda representa uma fração significante da potência consumida pelos dispositivos eletrônicos. A proposta deste trabalho é prover uma revisão das abordagens desenvolvidas com a finalidade de reduzir a potência dinâmica de circuitos integrados no nível de porta lógica utilizando a técnica Multi-VDD e, além disso, propor melhorias em uma das metodologias estudadas. A técnica Multi-VDD detecta as portas lógicas do circuito que podem ter suas tensões de alimentação reduzidas sem que violações de tempo sejam inseridas no circuito. Para manter a integridade dos sinais do circuito, eventualmente, células especiais chamadas conversores de nível precisam ser inseridas no circuito. O algoritmo proposto foi validado através de sua aplicação em circuitos do benchmark ISCAS85. Os resultados obtidos foram bastante satisfatórios atingindo em média uma redução de potência de 18,31% em relação ao consumo de potência dinâmica inicial quando se utilizou uma restrição de tempo menos conservadora, e de 4,27% com uma restrição de tempo conservadora

Testing an integrated circuit once it has been manufactured is required in order to identify faulty and fault-free circuits. As the complexity of integrated circuits increases so does the difficulty of creating efficient and high quality tests that can detect a variety of defect types that can occur throughout the manufacturing process. Three issues facing manufacturing test are the power consumed during testing, addressing different types of fault, and test data volume. In regards to the power consumed during testing, abnormal switching activity, far above that seen by functional operation, may occur due to the testing technique of scan insertion. While scan insertion greatly simplifies test generation for sequential circuits, it may lead to excessive switching activity due to the loading and unloading of scan data and when the scan cells are updated using functional clocks. This can potentially damage the circuit due to excessive heat or inadvertently fail a good circuit due to current supply demands beyond design specifications. Stuck-at tests detect when lines are shorted to either the power supply or ground. Open faults are broken connections within the circuit. Some open faults may not be detected by tests generated for stuck-at faults. Therefore tests may need to be generated in order to detect these open faults. The voltage on the open node is determined by circuit parameters. Due to the feature size of the circuit it may not be possible to determine these circuit parameters, making it very difficult or impossible to generate tests for open faults. Automated test equipment is used to apply test stimuli and observing the output response. The output response is compared to the known fault-free response in order to determine if it is faulty or fault-free. Thus, automated test equipment must store the test stimuli and the fault-free responses in memory. With increased integrated circuit complexity, the number of inputs, outputs, and faults increase, increasing the overall data required for testing. Automated test equipment is very expensive, proportional to the memory required to store the test stimuli and fault-free output response. Simply replacing automated test equipment is not cost effective. These issues in the manufacturing test of integrated circuits are addressed in this dissertation. First, a method to reduce power consumption in circuits which incorporate data volume reduction techniques is proposed. Second, a test generation technique for open faults which does not require knowledge of circuit parameters is proposed. Third, a technique to further reduce output data volume in circuits which currently incorporate output response compaction techniques is proposed. Experimental results for the three techniques show their effectiveness.

The interest in implementing energy-efficient digital circuits using micro and nanoelectromechanical resonator technology has increased significantly over the last decade given their lower energy consumption in comparison to complementary metal oxide-semiconductor circuits. In this thesis, multiple circuit designs based on micro and nanoelectromechanical beam resonators are presented. These circuits include a nano resonator-based flash style analog-to-digital converter, a 4-bit digital-to-analog converter, and a micro-resonator-based 7:3 counter, all among the key building blocks of a microcomputing system. Simulations and experimental results were obtained for all circuits. In general, the proposed circuits based on nanoelectromechanical resonators show up to 90% reduction in energy consumption compared to their complementary metal-oxide-semiconductor counterparts in MHz operation speeds, fulfilling requirements for many applications such as Internet of Things and biomedical devices.

Energy efficient memory designs are becoming increasingly important, especially for applications related to mobile video technology and machine learning. The growing popularity of smart phones, tablets and other mobile devices has created an exponential demand for video applications in today’s society. When mobile devices display video, the embedded video memory within the device consumes a large amount of the total system power. This issue has created the need to introduce power-quality tradeoff techniques for enabling good quality video output, while simultaneously enabling power consumption reduction. Similarly, power efficiency issues have arisen within the area of machine learning, especially with applications requiring large and fast computation, such as neural networks. Using the accumulated data knowledge from various machine learning applications, there is now the potential to create more intelligent memory with the capability for optimized trade-off between energy efficiency, area overhead, and classification accuracy on the learning systems. In this dissertation, a review of recently completed works involving video and machine learning memories will be covered. Based on the collected results from a variety of different methods, including: subjective trials, discovered data-mining patterns, software simulations, and hardware power and performance tests, the presented memories provide novel ways to significantly enhance power efficiency for future memory devices. An overview of related works, especially the relevant state-of-the-art research, will be referenced for comparison in order to produce memory design methodologies that exhibit optimal quality, low implementation overhead, and maximum power efficiency. / National Science Foundation / ND EPSCoR / Center for Computationally Assisted Science and Technology (CCAST)

A critical and important part of the medical diagnosis is the montioring of the biopotential signals. Patients are always connected to a bulky and mains-powered instrument. This not only restricts the mobility of the patients but also bring discomfort to them. Meanwhile, the measureing time can not last long thus affecting the effects of the diagnosis. Therefore, there is a high demand for low-power and small size factor ambulatory biopotential measurement systems. In addtion, the system can be configured for different biopotential applications.The ultimate goal is to implement a system that is both invisible and comfortable. The systems not onlyincrease the quality of life, but also sharply decrease the cost of healthcare delivery. In this paper, a continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biopsignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design of the critical transistors eliminates the need of chopping circuits. The front-end is pure analog without interference from digital parts like chopping and switch capacitor circuits. The chip is fabricated under SMIC 0.18 μm CMOS process. The input-referred noise of the system is only 1.19 μVrms (0.48-2000Hz).Although the power consumption is only 32.1 μW under 3V voltage supply, test results show that the chip can successfully extract biopotential signals.