Since the invention of wireless telegraphy by Marconi in 1897, wireless technology has not only been enhanced, but also has become an integral part of our everyday lives. The first wireless mobile phone appeared around 1980. It was based on first generation analog technology that involved the use of Frequency Division Multiple Access (FDMA) techniques. Ten years later, second generation (2G) mobiles were dependent on Time Division Multiple Access (TDMA) techniques and Code Division Multiple Access (CDMA) techniques. Nowadays, third generation (3G) mobile systems depend on CDMA techniques to satisfy the need for faster, and more capacious data transmission in mobile wireless networks. Wideband CDMA (WCDMA) has become the major 3G air interface in the world. WCDMA employs convolutional encoding to encode voice and MPEG4 applications in the baseband transmitter at a maximum frequency of 2<i>Mbps</i>. To decode convolutional codes, Andrew Viterbi invented the Viterbi Decoder (VD) in 1967. In 2G mobile terminals, the VD consumes approximately one third of the power consumption of a baseband mobile transceiver. Thus, in 3G mobile systems, it is essential to reduce the power consumption of the VD. Conceptually, the Register Exchange (RE) method is simpler and faster than the Trace Back (TB) method for implementing the VD. However, in the RE method, each bit in the memory must be read and rewritten for each bit of information that is decoded. Therefore, the RE method is not appropriate for decoders with long constraint lengths. Although researchers have focused on implementing and optimizing the TB method, the RE method is focused on and modified in this thesis to reduce the RE method's power consumption. This thesis proposes a novel modified RE method by adopting a <i>pointer</i> concept for implementing the survivor memory unit (SMU) of the VD. A pointer is assigned to each register or memory location. The contents of thepointer which points to one register is altered to point to a second register, instead of copying the contents of the first register to the second. When the pointer concept is applied to the RE's SMU implementation (modified RE), there is no need to copy the contents of the SMU and rewrite them, but one row of memory is still needed for each state of the VD. Thus, the VDs in CDMA systems require 256 rows of memory. Applying the pointer concept reduces the VD's power consumption by 20 percent as estimated by the VHDL synthesis tool and by the new power reduction estimation that is introduced in this work. The coding gain for the modified RE method is 2. 6<i>dB</i> at an SNR of approximately 10-3. Furthermore, a novel zero-memory implementation for the modified RE method is proposed. If the initial state of the convolutional encoder is known, the entire SMU of the modified RE VD is reduced to only one row. Because the decoded data is generated in the required order, even this row of memory is dispensable. The zero-memory architecture is called the MemoryLess Viterbi Decoder (MLVD), and reduces the power consumption by approximately 50 percent. A prototype of the MLVD with a one third convolutional code rate and a constraint length of nine is mapped into a Xilinx 2V6000 chip, operating at 25 <i>MHz</i> with a decoding throughput of more than 3<i>Mbps</i> and a latency of two data bits. The other problem of the VD which is addressed in this thesis is the Add Compare Select Unit (ACSU) which is composed of 128 butterfly ACS modules. The ACSU's high parallelism has been previously solved by using a bit serial implementation. The 8-bit First Input First Output (FIFO) register, needed for the storage of each path metric (PM), is at the heart of the single bit serial ACS butterfly module. A new, simply controlled shift register is designed at the circuit level and integrated into the ACS module. A chip for the new module is also fabricated.

La synthèse de fréquences est une fonction largement utilisée dans les émetteur-récepteurs radios. En général, la fonction synthèse de fréquence est réalisée à l’aide d’une boucle à verrouillage de phase utilisant des diviseurs de fréquence numériques. Cette thèse présente un nouveau type de diviseur de fréquence faisant appel à des mémoires D et son application à la synthèse de fréquences. Ce nouveau diviseur permet de repousser les limites des diviseurs numériques classiques à bascules D, en matière de fréquence maximale de fonctionnement et de consommation, tout en conservant leur souplesse d’utilisation. La première partie de cette thèse présente les techniques usuelles de réalisation des synthèses de fréquence et des diviseurs de fréquences, ainsi que le nouveau diviseur SRO à base de mémoires D, sujet de ces travaux. Une étude détaillée de ce diviseur est réalisée avec un premier modèle utilisant une approche numérique, puis un second plus réaliste faisant appel à une modélisation de type analogique. Cette étude démontre que ce nouveau diviseur SRO est capable de fonctionner à une fréquence plus élevée ou avec une consommation moindre, tout en réalisant les mêmes facteurs de division, que les diviseurs classiques à bascules D. La dernière partie de cette thèse présente plusieurs implémentations en technologies CMOS et BiCMOS de ST Microelectronics du diviseur SRO. En particulier son implémentation dans deux synthétiseurs de fréquences fractionnaires à 24 GHz montre son intérêt de part la réduction significative de consommation obtenue, tout en conservant une structure simple utilisant une surface de silicium réduite / Frequency synthesis is almost used in all RF transceivers, where this function is usually achieved by using phase-locked-loop circuits. Most often, the phase-locked-loop includes digital frequency dividers in the feedback that present high power dissipation and low maximum frequency at gigahertz frequencies. This thesis presents a versatile new D latch-based divider that improves these issues and its application to frequency synthesis. The first part presents several frequency synthesis techniques and theirs main characteristics. Then is described various classical frequency dividers and the proposed new D latch-based SRO divider. A detailed study of the SRO divider is presented with two approaches, the digital one and the analogue one. This study demonstrates the benefit of the SRO divider in terms of power dissipation and speed compared with the widely used D flip-flop based dividers. The last part presents several implementations of the SRO divider in CMOS and BiCMOS processes of ST Microelectronics. Particularly, the SRO divider was implemented in two 24 GHz fractional synthesizers, where it demonstrates its interest for reduction of power dissipation while using small silicon area.

La dernière décennie à vu l’explosion des technologies de communication sans fils. Les normes se sont multipliées de sorte que les fonctionnalités GSM, GPS, WIFI, Bluetooth et autres cohabitent parfois au sein du même terminal. Les réseaux de capteurs (Wireless area network WSN) incluant les réseaux de capteur WPAN (Wireless Personnel Area Network) seront amenés à jouer un rôle important dans l’environnement de demain au même titre que les normes sans fils grand public que nous venons de mentionner. Le déploiement de ces capteurs à grande échelle a été rendu possible par la réduction du coût de leur fabrication via la miniaturisation des procédés de fabrication propres à la technologie CMOS. Cependant, la consommation énergétique de ces circuits doit être très réduite permettant ainsi de fonctionner dans le cas où ces mêmes capteurs sont associés à une batterie compacte embarquée de durée de vie réduite. A défaut il serait nécessaire de pouvoir se contenter de l’énergie récupérable - en quantité limité - disponible dans l'environnement direct de ces capteurs. Cette contrainte de consommation électrique réduite ainsi que la nécessité de profiter au maximum de la miniaturisation du procédé CMOS amène à considérer la conception de circuits radio sous l'angle du faible encombrement surfacique et de la consommation statique la plus faible possible. Ces contraintes sont parfois contradictoires avec les architectures classiques connues de ces circuits radio constituants les capteurs déployés.es travaux présentés dans le cadre de cette thèse s’attachent à proposer des solutions afin de répondre à ces critères de consommation et de coût. Nous nous sommes intéressés au cas des amplificateurs faible bruit (Low Noise Amplifier – LNA) et à la possibilité de réaliser ce composant critique pour le lien RF sans utiliser d’inductance intégrées tout en limitant au maximum la consommation électrique. Plusieurs solutions innovantes ont été étudiées afin de répondre à cet objectif. Ces travaux nous ont conduit à la réalisation de plusieurs prototypes de circuits en technologie CMOS 65nm et 130nm qui permettent de comprendre les limites et les avantages d’une telle approche. La première partie présentera une première approche consistant à émuler une inductance à l’aide de composants actifs et ainsi à résoudre le problème de l’encombrement propre au inductance passives. Nous verrons en quoi cette approche peut présenter des limites pratiques pour une application radio. La seconde partie présentera la réalisation d’un LNA très basse consommation et large bande qui n’utilise pas d’inductance et présentant des performances améliorées vis à vis des topologies connues de LNA à faible consommation. Nous conclurons ensuite par les perspectives ouvertes suite à ces travaux et les autres approches possibles pour répondre aux contraintes de la basse consommation et du faible coût. / During the past decade the intense development of wireless technologies standard such as WIFI, GSM or Bluetooth reshaped the connectivity environment of any technology customers Among those standards, Wireless Sensor Networks (WSN) and Wireless Personal Area Network (WPAN) are expected to play a key role in our future environments. The large scale spreading of such sensors has been enabled through the strong cost optimization of modern CMOS technologies. The autonomy improvement of such sensor is however a primary concern to allow any kind of remote operation within the limitation of battery life. Even though the emerging energy harvesting domain offer energy friendly environments for such sensor, the electrical autonomy remain as a tight challenge to address. Those requirements of autonomy along with the context of CMOS technology development pushes sometimes fundamental contradictions between circuit's miniaturization and decreased power consumption. In this work, we propose solutions to address simultaneously those autonomy-miniaturization requirements. The study presented here is focused on Low Noise Amplifiers (LNA) and more precisely on the specific case of inductorless design of LNA. Several innovative solutions has been proposed and realized in 65nm & 130nm CMOS technologies in order to highlight the pros and the cons of such design approach. First part of this work is focused on the design of an active inductance to address the area occupation of narrow band system using inductors. We'll explain why such approach rises fundamental limits for radio application. Second part details the design of an ultra low power broadband LNA without inductors. The proposed circuits enable significant improvement in performance tradeoffs for such low power consumption in comparison with known design techniques. We will conclude with general perspectives and other possible design approaches.

L’objectif de cette thèse est d’étudier l’efficacité énergétique des stratégies basse consommation pour des plateformes représentatives. Principalement, nous nous intéresserons aux stratégies énergétiques pour des systèmes embarqués multicœur en étudiant le comportement de politiques logicielles qui permettent la réduction effective de l’énergie tout en répondant aux exigences applicatives. Le travail présenté dans ce mémoire vise à étudier des stratégies de gestion de la consommation pour des plateformes monoprocesseur puis multiprocesseur concrètes. L’approche utilisée pour cette étude fut basée sur des plateformes représentatives afin d’identifier les paramètres significatifs, aussi bien au niveau matériel qu’au niveau applicatif, à l’inverse de nombreux travaux dans lesquels ces paramètres sont assez peu pris en compte voir ignorés. Ce travail analyse et compare diverses expérimentations menées sur des politiques énergétiques basées sur des techniques DVFS (Dynamic Voltage and Frequency Scaling) et DPS (Dynamic Power Switching) et définit les conditions sous lesquelles ces stratégies sont efficaces. Ces expérimentations ont permis d’établir des conclusions remarquables qui peuvent servir de pré-requis lors de la définition de stratégies efficaces de gestion de la consommation. Ces résultats montrent également que pour obtenir des stratégies efficientes il est nécessaire de tenir compte du domaine applicatif. Enfin, il faut noter que les modèles de haut de niveau de consommation ont été définis sur la base des mesures effectuées et afin d’estimer les gains énergétiques dès les premières étapes d’un flot de conception. / The purpose of this study is to investigate how power management strategies can be efficiently exploited in actual platforms. Primarily, the challenges in multicore based embedded systems lies in managing the energy expenditure, determining the scheduling behavior and establishing methods to monitor power and energy, so as to meet the demands of the battery life and load requirements. The work presented in this dissertation is a study of low power-aware strategies in the practical world for single and multiprocessor platforms. The approach used for this study is based on representative multiprocessor platforms (real or virtual) to identify the most influential parameters, at hardware as well as application level, unlike many existing works in which these parameters are often underestimated or sometimes even ignored. The work analyzes and compares in detail various experimentations with different power policies based on Dynamic Voltage and Frequency Scaling (DVFS) and Dynamic Power Switching (DPS) techniques, and investigates the conditions at which these policies are effective in terms of energy savings. The results of these investigations reveal many interesting and notable conclusions that can serve as prerequisites for the efficient use of power management strategies. This work also shows the potential of advanced domain specific power strategies compared to real world available strategies that are general purpose based in their majority. Finally, some high level consumption models are derived from the different energy measurement results to let the estimation of power management benefits at early stages of a system development.

Objetivo: verificar os efeitos de intervenções fisioterapêuticas, laser de baixa potência (LBP) e exercícios físicos (EF), de forma associada ou isolada, na osteoartrite de joelhos (OAJ). Método: Ensaio clínico randomizado, controlado, cego. Participaram da pesquisa 60 indivíduos de ambos os sexos, idade entre 45 e 75 anos, com diagnóstico radiográfico de OAJ graus 1 a 3, os quais foram randomizados em quatro grupos: 1) Grupo controle (GC, n=15): pacientes com OAJ e sem tratamento; 2) Grupo laser (GL, n=15): pacientes com OAJ e tratados com LBP (808nm, 5,6J); 3) Grupo exercício (GE, n=15): pacientes com OAJ e tratados com EF; 4) Grupo laser e exercício (GLE, n=15): pacientes com OAJ e tratados com LBP e EF. As avaliações foram realizadas no Laboratório de Avaliação e Reabilitação do Equilíbrio, no início e após dois meses, incluindo o questionário WOMAC (dor, rigidez e função física); avaliação das variáveis espaço-temporais da marcha pelo equipamento GAITRite; avaliação do torque dos músculos extensores de joelho pelo dinamômetro isocinético Biodex e a funcionalidade (teste de transpor degrau e teste de levantar-se de uma cadeira) pelo equipamento Balance Master. O tratamento foi realizado durante dois meses, 2x por semana. Na análise estatística foi utilizado o teste de Wilcoxon (dados não paramétricos) e o teste Anova Two Way seguido do teste post hoc de Tukey (dados paramétricos), com nível de significância de 5%, usando o software SPSS. Resultados: no questionário WOMAC, houve diferença apenas na comparação pré e após 2 meses (intragrupo) para o GE nas variáveis: dor (p=0,006), função (p=0,01) e na pontuação total do WOMAC (p=0,01). Na marcha, na análise intragrupo, os grupos que receberam intervenção (GL, GE e GLE) apresentaram redução significativa apenas na duração da fase de apoio direito (p=0,014; p=0,011; p=0,035, respectivamente). Na avaliação intergrupo, ocorreu um aumento significativo na velocidade da marcha dos grupos que receberam intervenção (GL, GE e GLE) comparado ao GC (p=0,03; p=0,04 e p=0,005 respectivamente), na cadência ocorreu aumento apenas no GLE em comparação ao GC (0,009). Ainda na avaliação intergrupo, na duração da fase de apoio direito, os grupos GE (p=0,035) e GLE (p=0,003) apresentaram diminuição significativa em relação ao GC e na duração da fase de apoio único direito, apenas o GLE apresentou aumento significativo (p=0,04) em relação ao GC. Na análise isocinética do torque dos extensores de joelho, apenas na avaliação intergrupo após 2 meses, o membro inferior esquerdo apresentou aumento significativo nos grupos GE (p=0,03) e GLE (p=0,04) em relação ao GC. Na avaliação intragrupo da funcionalidade, apresentaram diminuição significativa (p=0,04) apenas o GLE no teste de transpor degrau (variável: tempo de movimento do membro direito) e apenas o GE (p=0,04) no teste de levantar-se da posição sentada (variável: tempo de transferência do movimento). Conclusão: de uma maneira geral, os grupos: GE e GLE apresentaram mais benefícios quando comparados aos grupos GC e GL, o que sugere que o EF deve ser incluído no tratamento da OAJ, podendo ser acrescido do LBP. / Objective: To verify the effects of physical therapy interventions, low level laser therapy (LLLT) and physical exercises (PE), in an associated or isolated way, on knee osteoarthritis (KOA). Method: Randomized, controlled and blind clinical trial. Sixty individuals, both sexes, aged 45 to 75 years, with radiographic diagnosis of KOA, grades 1 to 3, were randomly assigned into four groups: 1) Control group (CG, n=15): patients with KOA, without treatment; 2) Laser group (LG, n=15): patients with KOA, treated with LLLT (808nm, 5.6J); 3) Exercise group (EG, n=15): patients with KOA, treated with PE; 4) Laser and Exercise group (LEG, n=15): patients with KOA, treated with LLLT and PE. The evaluations were performed at Laboratory of Assessment and Rehabilitation of Equilibrium, in the beginning and after 2 months, including the WOMAC questionnaire (pain, stiffness and physical function); evaluation of spatiotemporal gait variables was performed on GAITRite equipment; evaluation of knee extensor muscle torque using the Biodex isokinetic dynamometer and the functionality (step up/over and sit-to-stand test) through the Balance Master equipment. The treatment was performed for 2 months, twice a week. In the statistical analysis, Wilcoxon test (non-parametric data), and Anova Two Way followed Tukey\'s post hoc test (parametric data) were used, with significance level of 5%, using SPSS software. Results: in the WOMAC questionnaire, mean difference only in the comparison intragroup for the EG in the variables: pain (p=0.006), physical function (p=0.01) and total WOMAC (p=0.01). Regarding gait variables, in the intragroup analysis, the only variable that presented a significant difference was the duration of the right support phase, and the LG, EG and LEG had a significant decrease in this variable (p=0.014, p=0.011, p=0.035, respectively) in relation to the pre-treatment period. In the intergroup evaluation, a significant increase in gait speed occurred in the groups: GL, GE and GLE compared to the CG (p=0.03, p=0.04 and p=0.005, respectively). In the cadence there was a significant increase only in the LEG compared to the CG (0.009). In the duration of the right support phase, the GE and GLE groups presented a significant decrease (p=0.035 and p=0.003, respectively) in relation to the CG. In the analysis of the duration of single right limb support, only the LEG presented a significant increase (p=0.04) in relation to the CG. In the isokinetic analysis of the torque of knee extensors, only in the intergroup evaluation after 2 months, the left lower limb presented significant increase in the EG (p=0.03) and LEG (p=0.04) groups in relation to the CG. In the step up/over test, in the intragroup evaluation, only the LEG showed a significant decrease (p=0.04) in the transfer time variable in the intragroup comparison. In the sit-to-stand test, in the variable of time of transfer, only the EG showed a significant decrease (p=0.04) in the intragroup comparison. Conclusion: in general, the groups: EG and LEG presented more benefits when compared to the GC and GL groups, this suggests that EF should be included in the treatment of KOA, and may be added to LLLT.

Estiramento muscular e outras desordens músculo esqueléticas são as principais causas de afastamento do trabalho e estão entre as lesões mais comuns que desabilitam os atletas. O objetivo do presente estudo foi de investigar os efeitos da Terapia Laser de Baixa Intensidade (infravermelha, 810nm) no estiramento do músculo esquelético induzido em ratos. Métodos: Ratos wistar machos foram anestesiados para a indução do estiramento muscular. O animal foi posicionado, em decúbito dorsal, sobre cortiça acoplada ao sistema de alongamento. O membro posterior direito foi firmemente preso com linha, que passa por uma roldana e se prende a um peso correspondente a 150% do peso corporal do animal. Esta linha foi fixada sobre o dorso da pata do animal, realizando uma flexão plantar, alongando o músculo tibial anterior da pata posterior direita do animal. O protocolo foi realizado uma única vez sendo que o animal recebeu a tração durante 20 minutos, descansou por 3 minutos e recebeu mais uma tração durante 20 minutos Os grupos tratados receberam a irradiação do Laser no local da indução, 1 horas após a lesão, para analisar o índice funcional, estudo eletrofisiológico, a proteína C reativa, o extravasamento plasmático, expressão gênica por real time RT-PCR e protéica por Western-Blott de COX-1 e COX-2, TNF-, IL 1, IL 6, IL 10 e histologia. Resultados e Discussão: A utilização da Terapia Laser de Baixa potência reduziu a inflamação e o dano muscular após o estiramento experimental, conduzindo a uma melhora significativa da atividade de caminhar. / Muscle strains and other musculoskeletal disorders are a leading cause of work absenteeism and are among the most common and often disabling injuries in athletes. The main objetive of this study was to investigate the effects of low level laser therapy (infrared, 810nm) on controlled muscle strain in rats. Method: Male wistar rats were anesthetized for controlled muscle strain induction. After one hour the rats were treated with low level laser therapy to analize the functional index, eletrofisiologic study, reactive c protein, plasmatic extravasation, real time RT-PCR gene expression and western blott analisis of COX-1, COX-2, TNF-, IL-1, IL-6, IL-10 and histology. Results and Discussion: After experimental induction of muscle strech, Low Level Laser Therapy was effective reducing inflammation and muscle damage, conducting a better walking activity.

O trabalho trata do projeto e do desenvolvimento de um processador de baixo consumo de potência, de forma simplificada, explorando técnicas de microarquitetura, para atingir menor consumo de potência. É apresentada uma sequência lógica de desenvolvimento, a partir de conceitos e estruturas básicas, até chegar a estruturas mais complexas e, por fim, mostrar a microarquitetura completa do processador. Esse novo modelo de processador é comparado com estudos prévios de três processadores, sendo o primeiro modelo síncrono, o segundo assíncrono e o terceiro uma versão melhorada do primeiro modelo, que inclui minimizações de registradores e circuitos. Uma nova metodologia de criação de padring de microcontroladores, baseada em reuso de informações de projetos anteriores, é apresentada. Essa nova metodologia foi criada para a rápida prototipagem e para diminuir possíveis erros na geração do código do padring. Comparações de resultados de consumo de potência e área são apresentadas para o processador desenvolvido e resultados obtidos com a nova metodologia de geração de padring também são apresentados. Para o processador, um modelo, no qual se utilizam múltiplos barramentos para minimizar o número de ciclos de máquina por instrução, é apresentado. Também foram ressaltadas estruturas que podem ser otimizadas e circuitos que podem ser reaproveitados para diminuir a quantidade de circuito necessário na implementação. Por fim, a nova implementação é comparada com os três modelos anteriores; os ganhos obtidos de desempenho com a implementação dessas estruturas foram de 18% que, convertidos em consumo de potência, representam economia de 13% em relação ao melhor caso dos processadores comparados. A tecnologia utilizada no desenvolvimento dos processadores foi CMOS 250nm da TSMC. / This work is a development and implementation of a low power processor in a simplified way, exploring microarchitecture techniques to achieve low power consumption. A logic sequence of design flow is presented, starting from basic concepts and circuit structures incrementing these concepts and structures to achieve a complex microarchitecture of a processor. A new methodology for microcontroller padring creations based in reuse of previous project information is presented. This new methodology was developed for fast prototyping and decreases the possible error in generation of microcontroler padring code creation. This new microarchitecture is compared with three previous processors, one is an original synchronous version, the second is an asynchronous version, and the third is based on the first model with register and circuit minimizations. Results of area and power consumption are compared with this new proposed architecture. The new model uses multiple buses with access timing tuned for different internal blocks. This timing tuning decrease the number of machine cycle necessary per instruction. In addition, it presents some macro block circuit partition and circuit reuse to minimize the circuit necessary for implementation. The gain obtained in performance with these new structures was 18%, converting to power consumption, it represent a decrease in 13% in relation with the best of three processor compared. The technology used in the development of these processors was CMOS 250nm from TSMC.

Durant ces vingt dernières années l'émergence des technologies MEMS a rendu possible l'intégration de capteurs au sein de systèmes complexes de taille réduite. Quelques-uns de ces capteurs se retrouvent dans des dispositifs tels que les téléphones mobiles, GPSs, ordinateurs portables… Il existe néanmoins une contrainte majeure, quand à l’utilisation de capteurs dans les applications fonctionnant sur batterie : leurs «consommation». En effet du fait de cette contrainte la plus part des capteurs développés de nos jours sont basés sur des modes de transduction capacitif limitant ainsi la consommation mais par la même occasion complexifiant lourdement la conception de l’élément sensible. Cette complexité de réalisation de l’élément sensible se répercute donc sur le prix du produit final. Le meilleur moyen de diminuer le prix de revient d’un capteur est l’utilisation d’une technologie de transduction qui permet de diminuer la complexité structurelle du capteur. La transduction résistive répond bien à ce problème, cependant les structures de conditionnement de signal les plus utilisées dissipent une puissance excessive. Cette thèse propose donc l’étude d’une structure électronique faible bruit / faible consommation innovante (le pont Actif) permettant le conditionnement de signaux issus de capteurs résistifs. Les critères d’évaluation du pont actif sont ici le gain, le bruit intrinsèque de l’électronique (facteur limitant de la résolution) et, le plus important, la consommation globale du capteur (éléments sensible + électronique de traitement). / Since resistive sensors exist, the Wheatstone bridge has been the most commonly used conditioningand read-out architecture. Even with the development of MEMS in the last decade, the Wheatstonebridge remains the preferred solution to transpose a physical magnitude into the electrical domain assoon as a resistive transduction method is used. Nevertheless the Wheatstone bridge introduces amajor issue for low-power sensors, the dependence of resolution to power consumption. Moreover,the output signal is directly proportional to the supply voltage. Finally, power consumption is theprice to pay for high resolution in a Wheatstone bridge.Low-power requirement, in mobile applications, is probably one of the main reasons to explain whycapacitive transduction has been preferred for many MEMS. Indeed, even if the fabrication process isoften more complex than for resistive sensors, the power consumption of capacitive transduction isfar below the one of dissipative resistor-based sensors.In order to extend the potential application of resistive MEMS, a power-efficient interface circuit isrequired. My PhD thesis deals with the design and manufacturing of an innovative conditioning andread-out interface for resistive MEMS sensor. The proposed structure includes a digital offsetcompensation for robustness to process, voltage, temperature variations, and/or analog to digitalconversion. Results demonstrate good resolution to power consumption ratio and a good immunityto environmental parameters. Experimental results on a fully integrated CMOS/MEMS sensor finallydemonstrate the efficiency of this promising read-out architecture called The active bridge.

Au sein de l'équipe « Microsystèmes » du LIRMM, plusieurs capteurs ont été développés basés sur des structures mécaniques ou thermiques pour réaliser des fonctions de transduction, et ce dans un contexte d'intégration de capteurs à l'aide de technologies microélectroniques standards (MOS). Ces capteurs sont majoritairement résistifs car simples à concevoir et économiques à fabriquer. Néanmoins, parmi leurs inconvénients majeurs, la consommation et le bruit sont les plus notables. Dans une thèse précédente, un circuit de conditionnement nouveau appelé ‘pont Actif' a été proposé. Ce circuit, présenté comme une ‘alternative' au traditionnel pont de Wheatstone, permet de diminuer le courant consommé tout en offrant une amplification importante du signal. Dans ce contexte, l'objectif de cette thèse est d'évaluer l'intérêt du pont Actif dans une application ‘capteur de température'. La mesure de la température est au cœur de très nombreuses applications. De nombreux instruments ont été mis au point, le plus connu restant le thermomètre à mercure. Aujourd'hui, les capteurs de température sont largement utilisés dans les systèmes de mesure, d'instrumentation ou les systèmes de contrôle. Compte tenu de l'étendu des domaines d'application, proposer, dans un contexte de systèmes embarqués, un capteur de température résistif très faible consommation, très performant et occupant une faible surface reste pertinent aujourd'hui. Après un tour d'horizon des solutions existantes concernant la mesure de la température, la première partie de la thèse introduit les principes de fonctionnement du pont Actif différentiel. Sur cette base, différentes déclinaisons de capteurs de température optimisés en termes de consommation sont proposées, modélisées et caractérisées. Ces études montrent que le point de polarisation du capteur est sensible aux variations du procédé de fabrication. Par conséquent, dans le but de contrôler le point de polarisation, nous avons mis en œuvre une conversion tension-courant. Finalement, le capteur a été intégré dans un modulateur Sigma Delta. Aussi, le principe de fonctionnement général du modulateur et l'implantation de la chaîne capteur à retour numérique sont présentés. Le manuscrit est clos par une synthèse des différents points abordés tout au long de ce travail. / Several sensors using standard microelectronic technologies (MOS) have been developed based on mechanical or thermal structures to perform transduction functions by the ‘Microsystems' Team of the LIRMM. These sensors are mainly resistive thanks to their design simplicity and low cost. However, one of their major problems, power consumption and noise are the most notable. In another thesis, a new conditioning circuit called 'Active Bridge' has been proposed. This circuit, presented as an 'alternative' to the traditional Wheatstone bridge, reduces considerably the power consumption while providing an important signal amplification. In this context, the objective of this thesis is to evaluate the usefulness of the Active Bridge in a temperature sensor application.The temperature measurement is at the heart of many applications. Many instruments have been developed, the best known remaining mercury thermometer. Today, the temperature sensors are widely used in measuring systems, instrumentation and control systems. Given the wide application areas, propose, in the context of embedded systems, a resistive temperature sensor ultra-low power, high performance and small remains relevant.After an overview of the existing solutions for this kind of application, the first part of the thesis introduces the principle of the differential Active Bridge. So, different architectures of temperature sensors optimized in terms of consumption are proposed, modeled and characterized. These studies show the dependency of the operating point of the sensor to the process and mismatch variations process. Therefore, in order to control the operating point, a voltage to current conversion has been implemented. Finally, the sensor has been integrated into a Sigma Delta modulator to implement a digital feedback. Finally, a conclusion of the issues and different results have been discussed as conclusion in this manuscript.

Made available in DSpace on 2016-03-22T17:26:08Z (GMT). No. of bitstreams: 1 leandro zafalon.pdf: 1268402 bytes, checksum: cd35030285126fa95b61d98c6a518798 (MD5) Previous issue date: 2008-08-08 / The main goal of this work is the implementation and analyzes of new array multiplier architectures. These new architectures were recently presented in the scientific community by including different power reduction techniques, such as the use of efficient adder circuits and the optimization of the dedicated multiplication structures that allow the multiplication operation in the radix 2m. The new multipliers operate in 2´s complement and keep the same regularity presented by a conventional array multiplier. The architectures operate in the radix 2m, where m represents the group of bits multiplied at a time. In a conventional array multiplier, where the multiplication is performed bit by bit, m assumes value equal 1 (radix 2 operation). In this work, the new multiplier architectures operate in different radices, leading to a reduction in the number of partial product lines, enabling higher performance and power reduction in the multipliers. The 16, 32 and 64 bit width multipliers were described in textual language (gate level), and the comparisons between the multipliers are preformed in terms of area, delay and power consumption by using SIS environment (for area and delay results) and SLS tool (for power consumption estimation). In this work we have applied the proposed optimized multipliers in digital filtering algorithms such as finite impulse response (FIR) and dedicated architecture for the LMS (Least Mean Square) adaptive filtering / O objetivo principal deste trabalho é a implementação e análise de novas arquiteturas de circuitos multiplicadores array digitais recentemente apresentados no meio cientifico com diferentes técnicas de redução de potência, tais como a utilização de eficientes estruturas de circuitos somadores, bem como a otimização dos blocos dedicados de multiplicação, que permitem a operação de multiplicação na base 2m. A proposta de novas arquiteturas consiste em operações de multiplicação em complemento de 2 e que mantenham a mesma regularidade de um multiplicador array convencional. As arquiteturas podem operar com números na base 2m, onde m representa o grupo de bits de multiplicação. Em um multiplicador array convencional, onde a operação de multiplicação é realizada bit a bit, o valor de m é igual a 1 (operação na base 2). Neste trabalho, são apresentadas novas arquiteturas de multiplicadores que operam em diferentes bases, o que permite a redução do número de linhas de produtos parciais, com impactos diretos no aumento de desempenho e redução do consumo de potência. A implementação dos diferentes circuitos multiplicadores foi realizada no nível textual (nível de portas lógicas), onde circuitos multiplicadores de 16, 32 e 64 bits são comparados em termos de parâmetros de área, atraso e consumo de potência utilizando os ambientes SIS (para valores de área e atraso) e SLS (para estimação de valores de consumo de potência). Como estudos de caso, as diferentes arquiteturas de circuitos multiplicadores propostas neste trabalho foram aplicadas em filtros digitais de resposta finita ao impulso (FIR) e em arquitetura dedicada de algoritmo de filtragem adaptativa LMS (Least Mean Square)