Actualmente, los sistemas encastados están creciendo a un ritmo impresionante y proporcionan cada vez aplicaciones más sofisticadas. Un conjunto de creciente importancia son los sistemas multimedia portátiles de tiempo real y los sistemas de comunicación de procesado digital de señal: teléfonos móviles, PDAs, cámaras digitales, consolas portátiles de juegos, terminales multimedia, netbooks, etc. Estos sistemas requieren computación específica de alto rendimiento, generalmente con restricciones de tiempo real y calidad de servicio (Quality of Service - QoS), que han de ejecutarse con un nivel bajo de consumo para extender la vida de la batería y evitar el calentamiento del dispositivo. También se requiere una arquitectura flexible para satisfacer las restricciones del "time-to-market". En consecuencia, los sistemas encastados necesitan una solución programable, de bajo consumo y alta capacidad de computación para satisfacer todos los requerimientos.Las arquitecturas de tipo Very Long Instruction Word parecen una buena solución ya que proporcionan el suficiente rendimiento a bajo consumo con la programabilidad requerida. Estas arquitecturas se asientan sobre el esfuerzo del compilador para extraer el paralelismo disponible a nivel datos y de instrucciones para mantener las unidades computacionales ocupadas todo el rato. Con la densidad de los transistores doblando cada 18 meses, están emergiendo arquitecturas cada vez más complejas con un alto número de recursos computacionales ejecutándose en paralelo. Con esta, cada vez mayor, computación paralela, el acceso a los datos se está convirtiendo en el mayor impedimento que limita la posible extracción del paralelismo. Para aliviar este problema, en las actuales arquitecturas, una unidad especial trabaja en paralelo con los principales elementos computacionales para asegurar una eficiente transmisión de datos: la Unidad Generadora de Direcciones (Address Generator Unit), que puede implementarse de diferentes formas.El propósito de esta tesis es probar que optimizar el proceso de la generación de direcciones es una manera eficiente de solucionar el proceso de acceder a los datos al mismo tiempo que disminuye el tiempo de ejecución y el consumo de energía.Esta tesis evalúa la efectividad de los diferentes dispositivos que actualmente se usan en los sistemas encastados, argumenta el uso de procesadores de tipo "very long instruction word" y presenta la infraestructura de compilador y exploración arquitectural usada en los experimentos. Esta tesis también presenta una clasificación sistemática de los generadores de direcciones, un repaso de las diferentes técnicas de optimización actuales acorde con esta clasificación y una metodología, usando técnicas ya publicadas, sistemática y óptima que reduce gradualmente la energía necesitada. También se introduce el entorno de trabajo que permite una exploración arquitectural sistemática y los métodos usados para obtener una unidad de generación de direcciones. Los resultados de este unidad de generación de direcciones reconfigurable se muestran en diferentes aplicaciones de referencia (benchmarks) y la metodología sistemática se muestra en una aplicación completa real. / Nowadays Embedded Systems are growing at an impressive rate and provide more and more sophisticated applications. An increasingly important set of embedded systems are real-time portable multimedia and digital signal processing communication systems: cellular phones, PDAs, digital cameras, handheld gaming consoles, multimedia terminals, netbooks, etc. These systems require high performance specific computations, usually with real-time and Quality of Service (QoS) constraints, which should run at a low energy level to extend battery life and avoid heating. A flexible system architecture is also required to successfully meet short time-to-market restrictions. Hence, embedded systems need a programmable, low power and high performance solution in order to deal with these requirements.Very Long Instruction Word architectures seem a good solution for providing enough computational performance at low-power with the required programmability to speed the time-to-market. Those architectures rely on compiler effort to exploit the available instruction and data parallelism to keep the data path busy all the time. With the density of transistors doubling each 18 months, more and more complex architectures with a high number of computational resources running in parallel are emerging. With this increasing parallel computation, the access to data is becoming the main bottleneck that limits the available parallelism. To alleviate this problem, in current embedded architectures, a special unit works in parallel with the main computing elements to ensure efficient feed and storage of the data: the Address Generator Unit, which comes in many flavors. The purpose of this dissertation is to prove that optimizing the process of address generation is an effective way of solving the problem of accessing data while decreasing execution time and energy consumption.As a first step, this thesis evaluates the effectiveness of different state-of-the-art devices commonly used in the embedded domain, argues for the use of very long instruction word processors and presents the compiler and architecture framework used for our experiments. This thesis also presents a systematic classification of address generators, a review of literature according to the classification of the different optimizations on the address generation process and a step-wise methodology that gradually reduces energy reusing techniques that already have been published. The systematic architecture exploration framework and methods used to obtain a reconfigurable address generation unit are also introduced.Results of the reconfigurable address generator unit are shown on several benchmarks and applications, and the complete step-wise methodology is demonstrated on a real-life example.

In wireless communication there is commonly much unnecessary communication made in directions not pointing towards the recipient. Normally omni directional antennas are being used which sends the same amount of energy in all directions equally. This waste of energy reduces the lifetime of battery powered units and causes more traffic collisions than necessary. One way of minimizing this wasted energy and traffic collisions, is to use another type of antenna called “smart antenna”. These antennas can use selectable radiation patterns depending on the situation and thus drastically minimize the unnecessary energy waste. Smart antennas also provide the ability to sense the direction of incoming signals which is favorable for physical layout mapping such as orientation. This thesis presents the prototyping of a new type of smart antenna called the SPIDA smart antenna. This antenna is a cheap to produce smart antenna designed for the 2.4 GHz frequency band. The SPIDA smart antenna can use sixty-four different signal patterns with the control of six separate directional modes, amongst these patterns are six single direction patterns, an omni-directional signal pattern and fifty-six combi-direction patterns. The thesis presents complete building instructions, evaluation data and functional drivers for the SPIDA smart antenna.

Significant advanced development in the field of communication has led many designers and healthcare professionals to look towards wireless communication for the treatment of dreadful diseases. Implant medical device offers many benefits, but design of implantable device at very low power combines with high data rate is still a challenge. However, this device does not rely on external source of power. So, it is important to conserve every joule of energy to maximize the lifetime of a device. Choice of modulation technique, frequency band and data rate can be analyzed to maximize battery life. In this thesis work, system level design of FSK and QPSK transmitter is presented. The proposed transmitter is based on direct conversion to RF architecture, which is known for low power application. Both the transmitters are designed and compared in terms of their performance and efficiency. The simulation results show the BER and constellation plots for both FSK and QPSK transmitter.

In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. This thesis work initially investigates and compares different structures of SAR control logics including the conventional structures and the delay line based controller. Additionally, it focuses on selection of suitable dynamic comparator architecture.  Based on this analysis, dynamic two-stage comparator is selected due to its energy efficiency and capability of working in low supply voltages. Eventually, based on these studies an ultra-low power 10-bit SAR ADC in 65 nm technology is designed. Simulation results predict that the ADC consumes 12.4nW and achieves an energy efficiency of 14.7fJ/conversion at supply voltage of 1V and sampling frequency of 1kS/s. It has a signal-to-noise-and-distortion (SINAD) ratio of 60.29dB and effective-number-of-bits (ENOB) of 9.72 bits. The ADC is functional down to supply voltage of 0.5V with proper performance and minimal power consumption of 6.28nW.

In this thesis, a Static Random Access Memory generator has been designed and implemented. The tool can generate memories of different sizes. The number of words that can be stored can be chosen among powers of 2 and the number of bits per word can be up to 48. The focus of the thesis was to find an adequate structure for the generated memories depending on the size, and develop a memory generator that implements the structures, which has been thoroughly done. The single circuits used in the generated memories can be substituted with better circuits as well as adapted to other processes. All circuits apart from a block decoder circuit have been developed. The memory generator was not supposed to automatically produce a complete layout, and some manual interventions on the memories generated by the tool are necessary. The tool requires to be developed further to minimise this manual intervention on the generated memories. The complete memories generated have not been tested because of their complexity, but tests on circuits as well as many parts of the memories have been carried out. During the thesis work, a large amount of tasks had to be carried out and a lot of issues had to be dealt with, which has been a problem. The tool used for the implementation has powerful features for both analog and digital electronic design, but has stability problems with large designs, which has been a big obstacle in this work.

In this master thesis, a behavioral VHDL model of a 1k Fast Fourier Transform (FFT) algorithm has been improved, first to make it synthesizable and second to obtain a low power consumption. The purpose of the thesis has not been to focus on the FFT algorithm itself or the theory behind it. Instead the aim has been to document and motivate the necessary modifications, to reach the stated requirements, and to discuss the results. The thesis is divided into sections so that the design flow closely can be followed from the initial FFT, down to the final architecture. The two major design steps covered are synthesis and power simulation. The synthesis process has been the most time consuming part of the thesis. The synthesis tool Cadence Ambit PKS was used. Throughout the synthesis, the modifications and solutions will be discussed and comparisons are continuously made between the different solutions and the initial FFT. The best solution will then be the starting point in the next design step, which is simulation of the design with respect to power consumption. This is done by using a simulation tool from Synopsys called NanoSim. Also here, every solution is tested and compared to each other, followed by a concluding discussion. The technology used to implement the design is a 0.35um CMOS process.

A dual-mode second-order Multirate Multibit Sigma Delta (MM-SD) modulator is implemented in a 90nm digital CMOS process for application in the baseband path of RF receivers. Low power consumption is achieved through a new integrator structure and a dedicated timing scheme along with aggressive capacitor scaling in the second stage of the modulator loop. Fabricated prototype achieves 68.6dB peak Signal-to-Noise and Distortion ratio (SNDR) in the 200 kHz GSM band and requires 1.1mA of total current from a 1.5V supply. This dual-mode design also achieves 42.8dB SNDR in the 1.94 MHz WCDMA band with only 1.9mA of total current consumption.

Multiple trends in computer architecture are beginning to collide as process technology reaches ever smaller feature sizes. Problems with managing power, access times across a die, and increasing complexity to sustain growth are now blocking commercial products like the Pentium 4. These problems also occur in the embedded system space, albeit in a slightly different form. However, as process technology marches on, today's high-performance space is becoming tomorrow's embedded space. New techniques are needed to overcome these problems. In this thesis, we propose a novel architecture called SoftCache to address these emerging issues for embedded systems. We reduce the on-die memory controller infrastructure which reduces both power and space requirements, using the ubiquitous network device arena as a proving ground of viability. In addition, the SoftCache achieves further power and area savings by converting on-die cache structures into directly addressable SRAM and reducing or eliminating the external DRAM. To avoid the burden of programming complexity this approach presents to the application developer, we provide a transparent client-server dynamic binary translation system that runs arbitrary ELF executables on a stripped-down embedded target. One drawback to such a scheme lies in the overhead of additional instructions required to effect cache behavior, particularly with respect to data caching. Another drawback is the power use when fetching from remote memory over the network. The SoftCache comprises a dynamic client-server translation system on simplified hardware, targeted at Intel XScale client devices controlled from servers over the network. Reliance upon a network server as a ``backing store' introduces new levels of complexity, yet also allows for more efficient use of local space. The explicitly software managed aspects create a cache of variable line size, full associativity, and high flexibility. This thesis explores these particular issues, while approaching everything from the perspective of feasibility and actual architectural changes.

The main objective of this research is to develop a pervasive wire sharing technique that can be easily applied across the entire range of on-chip interconnects in a very large scale integration (VLSI) system. A wave-pipelined multiplexed (WPM) routing technique that can be applied both intra-macrocell and inter-macrocell interconnects is proposed in this thesis. It is shown that an extensive application of the WPM routing technique can provide significant advantages in terms of area, power and performance. In order to study the WPM routing technique, a hierarchical approach is adopted. A circuit-level, system-level and physical-level analysis is completed to explore the limits and opportunities to apply WPM routing to current VLSI and future gigascale integration (GSI) systems. Design, verification and optimization of the WPM circuit and measurement of its tolerance to external noise constitute the circuit-level analysis. The physical-level study involves designing wire sharing-aware placement algorithms to maximize the advantages of WPM routing. A system-level simulator that designs the entire multilevel interconnect network is developed to perform the system-level analysis. The effect of WPM routing on a full-custom interconnect network and a semi-custom interconnect network is studied.

A micromachined magnetic field sensing system capable of measuring the direction of the Earths magnetic field has been fabricated, measured, and characterized. The system is composed of a micromachined silicon resonator combined with a permanent magnet, excitation and sensing coils, and a magnetic feedback loop. Electromagnetic excitation of the mechanical resonator enables it to operate with very low power consumption and low excitation voltage. The interaction between an external magnetic field surrounding the sensor and the permanent magnet generates a rotating torque on the silicon resonator disc, changing the effective stiffness of the beams and therefore the resonant frequency of the sensor. MEMS-based mechanically-resonant sensors, in which the sensor resonant frequency shifts in response to the measurand, are widely utilized. Such sensors are typically operated in their linear resonant regime. However, substantial improvements in resonant sensor performance can be obtained by designing the sensors to operate far into their nonlinear regime. This effect is illustrated through the use of a magnetically-torqued, rotationally-resonant MEMS platform. Platform structural parameters such as beam width and number of beams are parametrically varied subject to the constraint of constant small-deflection resonant frequency. Nonlinear performance improvement characterization is performed both analytically as well as with Finite Element Method (FEM) simulation, and confirmed with measurement results. These nonlinearity based sensitivity enhancement mechanisms are utilized in the device design. The complete magnetic sensing system consumes less than 200 microwatts of power in continuous operation, and is capable of sensing the direction of the Earths magnetic field. Such low power consumption levels enable continuous magnetic field sensing for portable electronics and potentially wristwatch applications, thereby enabling personal navigation and motion sensing functionalities. A total system power consumption of 138W and a resonator actuation voltage of 4mVpp from the 1.2V power supply have been demonstrated with capability of measuring the direction of the Earths magnetic field. Sensitivities of 0.009, 0.086, and 0.196 [mHz/(Hz and #903;degree)] for the Earths magnetic field were measured for 3, 4, and 6 beam structures, respectively.