New soybean lines have been developed with significantly higher oil, protein + oil and higher meal protein. These soybeans contain a VgD1 gene (highly active acyl-CoA:diacylglycerol acyltransferase, DGAT from Vernonia galamensis (VgDGAT1A) produces much higher oil synthesis and accumulation activity in soybean. Soybean with active DGAT from Vernonia galamensis (VgDGAT1A) has active TAG biosynthesis relative to other DGATs including from soybeans and Arabidopsis. DGATs catalyze the final step of TAG synthesis: DAG (diacylglycerol) + acyl-CoA → TAG + CoASH (Coenzyme A is notable for its role in the synthesis and oxidation of fatty acids, and the oxidation of pyruvate in the citric acid cycle). A thorough analysis of the major components in VgD1 lines, especially those of nutritional or anti-nutritional value including what else changed (decreased); and what remained at normal levels was conducted. A field study was conducted in Spindletop and Princeton KY, reviled no reduction in yield nor protein, and about 4 % (DW) more oil was obtained in Princeton and 2% (DW) in Spindeltop. No consistent reduction in the other seed composition.VgDGAT1A soybean lines indicated noticeably early maturation compared to the parental line. This is associated with higher expression of the flowering genes FT2 (FLOWERING LOCUS T2) and FT5 (FLOWERING LOCUS T5), for the high oil lines. A single recessive mutation in soybean (MIPS) myo-inositol 1-phosphate synthase, confers a seed phenotype of increase inorganic phosphate (Pi) crossed with high oil lines expressing a DGAT from Vernonia galamensis (VgDGAT1A) (VgD). The oil and protein were maintained compart to VgD. VgD X MIPS (VM), had 21.2, and 22 % oil in 2015, and 23.3 and 24.0 oil in 2016, and protein 46, 49 in 2015, and 37 and 39 % in 2016. Phosphate results suggesting the cross MV is still segregating for MIPS and more selection and planting are needed. Measurement of seed phosphate levels is an established technique for screening for low phytate mutants but to date, it has not been performed non-destructively from single soybean seeds. A protocol was developed greatly reducing the sample size thereby reducing the cost and time and saving a generation in the selection of low phytate mutant seeds based on the high Pi phenotype. Genotyping single seeds are useful in breeding and genetics while maintaining high germination rates. Nondestructive single-seed genomic DNA extraction protocols using 12 mg cotyledon tissue with a modified cetyl trimethyl ammonium bromide (CTAB) technique and a commercial seed DNA extraction kit using 1 mg cotyledon tissue were developed for dry soybean seeds and cross-verified with leaf DNA analysis.

<p>Nowadays, FPGAs are large enough to host entire system-on-chip designs, wherein a soft core processor is often an integral part. High performance of the processor is always desirable, so there is an interest in finding faster solutions.This report aims to describe the work and results performed by Karl Bengtson and Olof Andersson at ISY. The task was to continue the development of a soft core microprocessor, originally created by Andreas Ehliar. The first step was to decide a more widely adopted instruction set for the processor. The choice fell upon the MIPS32 instruction set. The main work of the project has been focused on implementing support for MIPS32, allowing the processor to execute MIPS assembly language programs. The development has been done with speed optimization in mind. For every new function, the effects on the maximum frequency has been considered, and solutions not satisfying the speed requirements has been abandoned or revised.The performance has been measured by running a benchmark program—Coremark. Comparison has also been made to the main competitors among soft core processors. The results were positive, and reported a higher Coremark score than the other processors inthe study. The processor described herein still lacks many essential features. Nevertheless, the conclusion is that it may be possible to create a competitive alternative to established soft processors.</p> / <p>FPGAer används idag ofta för stora inbyggda system, i vilka en mjuk processor ofta spelar en viktig roll. Hög prestanda hos processorn är alltid önskvärt, så det finns ett intresse i att hitta snabbare lösningar. Denna rapport skall beskriva det arbete och de resultat som uppnåtts av Karl Bengtson och Olof Andersson på ISY. Uppgiften var att fortsätta utvecklandet av en mjuk processor, som ursprungligen skapats av Andreas Ehliar. Första steget var att välja ut en mer allmänt använd instruktionsuppsättning för processorn. Valet föll på instruktionsuppsättningsarkitekturen MIPS32. Projektets huvutarbete har varit fokuserat på att implementera stöd för MIPS32, vilket ger processorn möjlighet att köra assemblerprogram för MIPS.Utvecklingen har gjorts med hastighetsoptimering i beaktning. För varje ny funktion har dess effekter på maxfrekvensen undersökts,och lösningar som inte uppfyllt hastighetskraven har förkastats eller reviderats. Prestandan har mätts med programmet Coremark. Det har också gjorts jämförelser med huvudkonkurrenterna bland mjuka processorer. Resultaten var positiva, och rapporterade ett högre Coremarkpoäng än de andra processorerna i studien. Slutsatsen är att det ärmöjligt att skapa ett alternativ till de etablerade mjuka processorerna, men att denna processor fortfarande saknar väsentliga funktioner som behövs för att utgöra en mogen produkt.</p>

This thesis demonstrate how pipelining in a RISC processor is achieved by implementing a subset of MIPS R2000 instructions on FPGA. Pipelining, which is one of the primary concepts to speed up a microprocessor is emphasized throughout this thesis. Pipelining is fundamentally invisible for high level programming language user and this work reveals the internals of microprocessor pipelining and the potential problems encountered while implementing pipelining. The comparative and quantitative flow of this thesis allows to understand why pipelining is preferred instead of other possible implementation schemes. The methodology for programmable logic development and the capabilities of programmable logic devices are also given as background information. This thesis can be the starting point and reference for programmers who are willing to get familiar with microprocessors and pipelining.

Atualmente, pode-se observar que a Lei de Moore vem estagnando. A freqüência de operação já não cresce da mesma forma, e a potência consumida aumenta drasticamente em processadores de propósito geral. Ao mesmo tempo, sistemas embarcados vêm se tornando cada vez mais heterogêneos, caracterizados por uma grande quantidade de modelos computacionais diferentes, sendo executados em um mesmo dispositivo. Desta maneira, como novas tecnologias que irão substituir totalmente ou parcialmente o silício estão surgindo, novas soluções arquiteturais são necessárias. Apesar de sistemas reconfiguráveis já terem demonstrado serem candidatos em potencial para os problemas supracitados, ganhos significativos de desempenho são alcançados apenas em programas que manipulam dados massivamente, não representando a realidade dos sistemas atuais. Ademais, o seu uso em alta escala ainda está limitado à utilização de ferramentas ou compiladores que, claramente, não mantêm a compatibilidade de software e a reutilização do código binário já existente. Baseando-se nestes fatos, a presente tese propõe uma nova técnica para, utilizando um sistema reconfigurável, otimizar tanto programas orientados a dados como aqueles orientados a controle, sem a necessidade de modificação do código fonte ou binário. Para isto, um algoritmo de Tradução Binária, que trabalha em paralelo ao processador, foi desenvolvido. O mecanismo proposto é responsável pela transformação de seqüências de instruções, em tempo de execução, para serem executadas em uma unidade funcional reconfigurável de granularidade grossa, suportando execução especulativa. Desta maneira, é possível aproveitar as vantagens do uso da lógica combinacional para aumentar o desempenho e reduzir o gasto de energia, mantendo a compatibilidade binária em um processo totalmente transparente. Três diferentes estudos de caso foram feitos: os processadores Java e MIPS R3000 – representando o campo de sistemas embarcados – e o conjunto de ferramentas Simplescalar, que simula um processador superescalar baseado no MIPS R10000 – representando o mercado de processadores de propósito geral. / As Moore’s law is losing steam, one already sees the phenomenon of clock frequency reduction caused by the excessive power dissipation in general purpose processors. At the same time, embedded systems are getting more heterogeneous, characterized by a high diversity of computational models coexisting in a single device. Therefore, as innovative technologies that will completely or partially replace silicon are arising, new architectural alternatives are necessary. Although reconfigurable computing has already shown to be a potential solution for such problems, significant speedups are achieved just in very specific dataflow oriented software, not representing the reality of nowadays systems. Moreover, its wide spread use is still withheld by the need of special tools and compilers, which clearly preclude software portability and reuse of legacy code. Based on all these facts, this thesis presents a new technique using reconfigurable systems to optimize both control and dataflow oriented software without the need of any modification in the source or binary codes. For that, a Binary Translation algorithm has been developed, which works in parallel to the processor. The proposed mechanism is responsible for transforming sequences of instructions at runtime to be executed on a dynamic coarse-grain reconfigurable array, supporting speculative execution. This way, it is possible to take advantage of using pure combinational logic to speed up the execution, maintaining full binary compatibility in a totally transparent process. Three different case studies were evaluated: a Java Processor and a MIPS R3000 – representing the embedded systems field – and the Simplescalar Toolset, a widely used toolset that simulates a superscalar architecture based on the MIPS R10000 processor – representing the general-purpose market.

Atualmente, pode-se observar que a Lei de Moore vem estagnando. A freqüência de operação já não cresce da mesma forma, e a potência consumida aumenta drasticamente em processadores de propósito geral. Ao mesmo tempo, sistemas embarcados vêm se tornando cada vez mais heterogêneos, caracterizados por uma grande quantidade de modelos computacionais diferentes, sendo executados em um mesmo dispositivo. Desta maneira, como novas tecnologias que irão substituir totalmente ou parcialmente o silício estão surgindo, novas soluções arquiteturais são necessárias. Apesar de sistemas reconfiguráveis já terem demonstrado serem candidatos em potencial para os problemas supracitados, ganhos significativos de desempenho são alcançados apenas em programas que manipulam dados massivamente, não representando a realidade dos sistemas atuais. Ademais, o seu uso em alta escala ainda está limitado à utilização de ferramentas ou compiladores que, claramente, não mantêm a compatibilidade de software e a reutilização do código binário já existente. Baseando-se nestes fatos, a presente tese propõe uma nova técnica para, utilizando um sistema reconfigurável, otimizar tanto programas orientados a dados como aqueles orientados a controle, sem a necessidade de modificação do código fonte ou binário. Para isto, um algoritmo de Tradução Binária, que trabalha em paralelo ao processador, foi desenvolvido. O mecanismo proposto é responsável pela transformação de seqüências de instruções, em tempo de execução, para serem executadas em uma unidade funcional reconfigurável de granularidade grossa, suportando execução especulativa. Desta maneira, é possível aproveitar as vantagens do uso da lógica combinacional para aumentar o desempenho e reduzir o gasto de energia, mantendo a compatibilidade binária em um processo totalmente transparente. Três diferentes estudos de caso foram feitos: os processadores Java e MIPS R3000 – representando o campo de sistemas embarcados – e o conjunto de ferramentas Simplescalar, que simula um processador superescalar baseado no MIPS R10000 – representando o mercado de processadores de propósito geral. / As Moore’s law is losing steam, one already sees the phenomenon of clock frequency reduction caused by the excessive power dissipation in general purpose processors. At the same time, embedded systems are getting more heterogeneous, characterized by a high diversity of computational models coexisting in a single device. Therefore, as innovative technologies that will completely or partially replace silicon are arising, new architectural alternatives are necessary. Although reconfigurable computing has already shown to be a potential solution for such problems, significant speedups are achieved just in very specific dataflow oriented software, not representing the reality of nowadays systems. Moreover, its wide spread use is still withheld by the need of special tools and compilers, which clearly preclude software portability and reuse of legacy code. Based on all these facts, this thesis presents a new technique using reconfigurable systems to optimize both control and dataflow oriented software without the need of any modification in the source or binary codes. For that, a Binary Translation algorithm has been developed, which works in parallel to the processor. The proposed mechanism is responsible for transforming sequences of instructions at runtime to be executed on a dynamic coarse-grain reconfigurable array, supporting speculative execution. This way, it is possible to take advantage of using pure combinational logic to speed up the execution, maintaining full binary compatibility in a totally transparent process. Three different case studies were evaluated: a Java Processor and a MIPS R3000 – representing the embedded systems field – and the Simplescalar Toolset, a widely used toolset that simulates a superscalar architecture based on the MIPS R10000 processor – representing the general-purpose market.

El documento digital no refiere asesor / Publicación a texto completo no autorizada por el autor / Desarrolla el diseño de un procesador segmentado con la finalidad de ayudar a los estudiantes en el aprendizaje del desempeño de este tipo de procesadores, principalmente cuando se presentan conflictos con relación a la secuencia de instrucciones utilizadas y sus dependencias. Para ello se utilizan técnicas hardware, tales como el adelantamiento de datos, inserción de burbujas, y anticipación de riesgos. Estos métodos se aplican para la arquitectura MIPS que consta de una segmentación de 5 etapas y cumple con las características de la arquitectura ISA tipo RISC empleada ampliamente en la temática de “Arquitectura de Computadoras”. El método empleado es desarrollar cada vez una nueva versión del procesador adaptado para solucionar el nuevo paradigma mostrando la mejora en su desempeño luego de hacerlo, así tendremos una versión que muestra la solución por riesgos de dependencia de datos. Otra versión del procesador para el caso en que una instrucción dependa del dato de una instrucción de carga, para finalmente realizar una última versión que solucione las dependencias debido a las bifurcaciones, que vienen a ser las más características y que presenta dificultad de asimilar en esta parte de la temática, tanto por la poca afición a la lectura del estudiantado como a la baja comprensión lectora que se tiene. El proceso de ver los eventos y simularlos más que solo verlos estáticamente permitirá una mejor y rápida comprensión de estos fenómenos así como su interacción al modificar los programas y el hardware del procesador respectivo. / Tesis

This work aims at improving an existing soft microprocessor core optimized for Xilinx Virtex®-4 FPGA. Instruction and data caches will be designed and implemented. Interrupt support will be added as well, preparing the microprocessor core to host operating systems. Thorough verification of the added modules is also emphasized in this work. Maintaining core clock frequency at its maximum has been the main concern through all the design and implementation steps.

Nowadays, FPGAs are large enough to host entire system-on-chip designs, wherein a soft core processor is often an integral part. High performance of the processor is always desirable, so there is an interest in finding faster solutions.This report aims to describe the work and results performed by Karl Bengtson and Olof Andersson at ISY. The task was to continue the development of a soft core microprocessor, originally created by Andreas Ehliar. The first step was to decide a more widely adopted instruction set for the processor. The choice fell upon the MIPS32 instruction set. The main work of the project has been focused on implementing support for MIPS32, allowing the processor to execute MIPS assembly language programs. The development has been done with speed optimization in mind. For every new function, the effects on the maximum frequency has been considered, and solutions not satisfying the speed requirements has been abandoned or revised.The performance has been measured by running a benchmark program—Coremark. Comparison has also been made to the main competitors among soft core processors. The results were positive, and reported a higher Coremark score than the other processors inthe study. The processor described herein still lacks many essential features. Nevertheless, the conclusion is that it may be possible to create a competitive alternative to established soft processors. / FPGAer används idag ofta för stora inbyggda system, i vilka en mjuk processor ofta spelar en viktig roll. Hög prestanda hos processorn är alltid önskvärt, så det finns ett intresse i att hitta snabbare lösningar. Denna rapport skall beskriva det arbete och de resultat som uppnåtts av Karl Bengtson och Olof Andersson på ISY. Uppgiften var att fortsätta utvecklandet av en mjuk processor, som ursprungligen skapats av Andreas Ehliar. Första steget var att välja ut en mer allmänt använd instruktionsuppsättning för processorn. Valet föll på instruktionsuppsättningsarkitekturen MIPS32. Projektets huvutarbete har varit fokuserat på att implementera stöd för MIPS32, vilket ger processorn möjlighet att köra assemblerprogram för MIPS.Utvecklingen har gjorts med hastighetsoptimering i beaktning. För varje ny funktion har dess effekter på maxfrekvensen undersökts,och lösningar som inte uppfyllt hastighetskraven har förkastats eller reviderats. Prestandan har mätts med programmet Coremark. Det har också gjorts jämförelser med huvudkonkurrenterna bland mjuka processorer. Resultaten var positiva, och rapporterade ett högre Coremarkpoäng än de andra processorerna i studien. Slutsatsen är att det ärmöjligt att skapa ett alternativ till de etablerade mjuka processorerna, men att denna processor fortfarande saknar väsentliga funktioner som behövs för att utgöra en mogen produkt.

Un polymère à empreintes moléculaires (MIP) est un récepteur synthétique supramoléculaire, un matériau possédant des cavités pouvant reconnaître spécifiquement une molécule cible. Il est synthétisé en mettant en contact la molécule cible, avec un mélange de monomères fonctionnels et réticulants qui permettent d'obtenir un réseau polymérique tridimensionnel rigide. L'élimination de la molécule empreinte laissera des sites vides complémentaires de cette dernière. Ces cavités sont maintenant capables de la recapturer spécifiquement. Ces polymères sont utilisés dans les domaines tels que l’extraction en phase solide, la chromatographie d’affinité, la catalyse enzymatique, les biocapteurs et la vectorisation des médicaments. Bien que le concept des MIPs a pour origine les travaux réalisés sur des matériaux sol-gel imprimés dans les années 1930, ces derniers sont restés dans l’ombre jusqu’à l'introduction de polymères organiques imprimés plus versatiles. Par rapport aux MIPs organiques, les MIPs sol-gel présentent quelques avantages comme une plus grande stabilité thermique, une meilleure compatibilité avec l'eau et une plus grande porosité. Dans cette thèse, nous avons développé des MIPs organiques et des MIPs sol-gel pour leur application en cosmétologie et pour la vectorisation de médicaments. Dans la première partie, nous présentons des MIPs pouvant adsorber d’une façon spécifique l’acide oléique (OA), un biomarqueur de l’état pelliculaire sur le cuir chevelu. Pour la préparation des MIPs organiques, nous avons employé plusieurs monomères basiques dont l’acryloylaminobenzamidine (AB), que nous avons tout spécialement synthétisé. Tous les MIPs pouvaient lier l’OA mais beaucoup d’interaction non-spécifique était observé. D’autre part, les MIPs sol-gel présentaient une bonne reconnaissance spécifique et une capacité élevée pour OA; par exemple, un MIP de composition OA:APTES:TEOS = 1:1.6:1.7 pouvait adsorber 625 μmol.g-1 de OA dans le sébum artificiel. Des tests pour capturer l’OA sur le stratum corneum et la peau reconstruite (Episkin) ont également été effectués. La pénétration de l’OA sur les deux types de peau était plus faible en présence de MIP que de NIP. Les MIPs comme matériaux désodorisants font l’objet de la deuxième partie de cette thèse. Des MIPs pouvant adsorber les précurseurs de molécules malodorantes comme les conjugués glutamine des acides (E)-3-méthyl-2-hexénoïque (3M2H) et 3-hydroxy-3-méthyl-hexanoïque (3H3MH) ont été préparés. Le N-hexanoyl glutamine et le N-hexanoyl glutamate ont été utilisés comme template. Nous observons que le MIP synthétisé avec AB comme monomère fonctionnel possède la plus grande capacité d'adsorption pour le N-hexanoyl glutamine, ainsi que pour les précurseurs glutamines des molécules malodorantes. Des résultats préliminaires et très prometteurs ont également été obtenus dans la sueur. La dernière partie de cette thèse concerne des MIPs pour la vectorisation de médicaments. L'acide salicylique (SA) est un médicament efficace utilisé dans le traitement de l’acné. Des MIPs organiques et sol-gel contre SA ont été synthétisés. Les MIPs sol-gel ont une plus grande capacité d’adsorption, 180 μmol.g-1, que les MIPs organiques et ils lient le SA sept fois plus que le NIP. Les tests de relargage du SA ont été effectués dans plusieurs milieux, avec la plus grande efficacité dans l’eau pure. En conclusion, les applications de MIPs en cosmétologie et en vectorisation de médicaments ont étés étudiés. Nos résultats montrent que les MIPs sol-gel sont les plus appropriés pour ce type de travail. / Molecularly imprinted polymers (MIPs) are tailor-made synthetic receptors possessing specific cavities for a given target molecule. They are produced by introducing, into the polymer precursors, guest molecules that act as templates at the molecular level. Interacting and cross-linking monomers are then copolymerized to form a cast-like shell. After removal of the template, cavities complementary to the template in size, shape and position of functional groups are revealed in the polymer, which can now specifically bind the template. Thanks to these specific molecular recognition properties, MIPs have found applications in areas like bio sensors, solid phase extraction, affinity chromatography, catalysis, and drug delivery. Although the MIP concept originated from imprinted silica in the 1930s, imprinted sol-gel materials received little attention afterwards due to the introduction of the more versatile organic polymers as imprinting matrix. However, compared to organic polymers, sol-gels possess higher thermal stability, better water compatibility and larger inner surface area. There have been many applications to biomolecules in aqueous conditions with sol-gel imprinting materials. In this thesis, we have developed organic and silica sol-gel MIPs for applications in cosmetics and drug delivery. MIPs able to adsorb the dandruff-inducing molecule oleic acid (OA) were produced via both the organic and inorganic routes. In the organic MIPs synthesis, different positively charged monomers were used, one of which, acryloyl aminobenzamidine, was specifically synthesized. Although some binding of oleic acid was obtained, specificity and capacity of these polymers were not satisfying. Sol-gel MIPs, on the other hand, exhibited good specific recognition and high binding capacity for OA. A MIP of the composition OA:APTES:TEOS= 1:1.6:1.7 yielded a capacity of 625 μmol.g-1 in artificial sebum. Furthermore, tests were carried out to capture OA on stratum corneum and reconstructed skin (Episkin). Less penetration of OA was observed in the presence of a MIP than with a non-imprinted control polymer. Deodorant materials are another topic of this thesis. MIPs that are able to adsorb certain precursors of odorant molecules, the glutamine conjugates of (E)-3-methyl-2-hexenoic acid (3M2H) and 3-hydroxy-3-methyl-hexanoic acid (3H3MH) were prepared. N-hexanoyl glutamine and N-hexanoyl glutamate were used as templates. After optimization of the MIP composition, we found that MIPs synthesized with acryloyl aminobenzamidine as functional monomer had the highest adsorption capacity for N-hexanoyl glutamine, and also recognised the glutamine targets of 3M2H and 3H3MH. Some preliminary promising binding results were obtained in artificial sweat. The third part of this work concerns a drug delivery MIP. Salicylic acid (SA) is a drug used to treat acne. SA-imprinted polymers were prepared via both organic imprinting and the sol-gel process.Compared to organic MIPs, sol-gel MIPs have a higher capacity, 180 μmol.g-1, and 7 times higher binding than to a non-imprinted control polymer was observed. Release tests were carried out in different aqueous media, the most efficient drug release was observed in pure water. In conclusion, applications of molecularly imprinted polymers for cosmetics and drug delivery have been investigated. Our results demonstrate the great potential of in particular sol-gel MIPs for these purposes.

The objective of this research was to isolate genes encoding isoforms of the enzyme D-myo-inositol 3-phosphate synthase (MIPS, E.C. 5.5.1.4) from soybean and to characterize their expression, especially with respect to their involvement in phytic acid biosynthesis. A MIPS-homologous cDNA, designated GmMIPS1, was isolated via PCR using total RNA from developing seeds. Southern blot analysis and examination of MIPS-homologous soybean EST sequences suggested that GmMIPS1 is part of a multigene family of at least four similar members. The sequences of promoter and genomic regions of GmMIPS1 and GmMIPS2 revealed a high degree of sequence conservation. Northern and western blot analyses showed that MIPS transcript and protein are abundantly expressed early in seed development. Immunolocalization of MIPS protein in developing seeds confirmed expression of MIPS early in seed development and correlated MIPS protein accumulation in soybean seed tissue with tissues in which phytic acid is known to accumulate. The promoter region of GmMIPS1 was isolated and analyzed for possible seed-specificity using promoter:GUS fusions. Two GmMIPS1 promoter fragments were capable of conferring GUS expression when bombarded directly into developing soybean seeds. However, preliminary bombardment experiments into soybean cell suspension culture indicated that both promoter fragments drove expression of GUS in undifferentiated tissue, indicating a potential lack of seed-specificity. / Master of Science