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The goal of this dissertation is to extend the state of the art in real-time scheduling algorithms to achieve energy efficiency. Currently, Pfair scheduling is one of the few scheduling frameworks which can optimally schedule a periodic real-time taskset on a multiprocessor platform. Despite the theoretical optimality, there exist large concerns about efficiency and applicability of Pfair scheduling in practical situations. This dissertation studies and proposes solutions to such efficiency and applicability concerns. This dissertation also explores temperature aware energy management in the domain of real-time scheduling. The thesis of this dissertation is: the implementation efficiency of Pfair scheduling algorithms can be improved. Further, temperature awareness of a real-time system can be improved while considering variation of task execution times to reduce energy consumption. This thesis is established through research in a number of directions. First, we explore the applicability of Dynamic Voltage and Frequency Scaling (DVFS) feature in the underlying platform, within Pfair scheduled systems. We propose techniques to reduce energy consumption in Pfair scheduling by using DVFS. Next, we explore the problem of quantum size selection in Pfair scheduled system so that runtime overheads are minimized. We also propose a hardware design for a central Pfair scheduler core in a multiprocessor system to minimized the overheads and energy consumption of Pfair scheduling. Finally, we propose a temperature aware energy management scheme for tasks with varying execution times.

High performance systems have been widely adopted in many fields and the demand for better performance is constantly increasing. And the need of powerful yet flexible systems is also increasing to meet varying application requirements from diverse domains. Also, power efficiency in high performance computing has been one of the major issues to be resolved. The power density of core components becomes significantly higher, and the fraction of power supply in total management cost is dominant. Providing dependability is also a main concern in large-scale systems since more hardware resources can be abused by attackers. Therefore, designing high-performance, power-efficient and secure systems is crucial to provide adequate performance as well as reliability to users. Adhering to using traditional design methodologies for large-scale computing systems has a limit to meet the demand under restricted resource budgets. Interconnecting a large number of uniprocessor chips to build parallel processing systems is not an efficient solution in terms of performance and power. Chip multiprocessor (CMP) integrates multiple processing cores and caches on a chip and is thought of as a good alternative to previous design trends. In this dissertation, we deal with various design issues of high performance multiprocessor systems based on CMP to achieve both performance and power efficiency while maintaining security. First, we propose a fast and secure off-chip interconnects through minimizing network overheads and providing an efficient security mechanism. Second, we propose architectural support for fast and efficient memory protection in CMP systems, making the best use of the characteristics in CMP environments and multi-threaded workloads. Third, we propose a new router design for network-on-chip (NoC) based on a new memory technique. We introduce hybrid input buffers that use both SRAM and STT-MRAM for better performance as well as power efficiency. Simulation results show that the proposed schemes improve the performance of off-chip networks through reducing the message size by 54% on average. Also, the schemes diminish the overheads of bounds checking operations, thus enhancing the overall performance by 11% on average. Adopting hybrid buffers in NoC routers contributes to increasing the network throughput up to 21%.

[pt] O sistema operacional MINIX é uma nova implementação do sistema UNIX, versão 7, feito para fins didáticos. Ele está formado por uma coleção de processos, estruturados em 4 niveis: administração de processos, processos básicos do sistema, processos servidores de memória e arquivos, e processos usuários. A presente dissertação descreve o transporte do sistema MINIX, do microcomputador IBM PC XT para o computador CYGNUS do laboratório de Sistema de Computação do Departamento de Engenharia Elétrica da PUC/RJ, o qual possui uma arquitetura baseada em processadores da linha Motorola (68010 e 68020). O trabalho do transporte, constituiu em adaptar o hardware do CYGNUS para receber o sistema operacional MINIX, reprojetar o MINIX para o hardware do CYGNUS, e transportar o MINIX em forma completa, para seu novo ambiente de execução. / [en] The MINIX operating System is a new implementation of the UNIX operating system version 7, designed for didactic purposes. It is arranged as a collection of processes, structured in 4 levels: process management, system basic processes, memory and file server processes, and user processes. This work describes the transport of the MINIX system from the IBM PC XT microcomputer to te CYGNUS computer, which was developed in the Computer System Laboratory of the Electrical Engineering Department of PUC/RJ, with an architecture based on Motorola processors (68010 and 68020). The task of transporting the system, consisted in adjusting the CYCNUS hardware to accept the MINIX, redesigning the MINIX for the CYGNUS hardware, and finaly, in transporting the MINIX in its complete form to its new execution environment.

[pt] O sistema CYGNUS é um computador multiprocessador de memória compartilhada e arquitetura modular, baseado nos processadores da família Motorola MC68000, que vem sendo desenvolvido pelos Departamentos de Engenharia Elétrica e Informática da PUC/RJ. O presente trabalho consiste do projeto e implementação de dois módulos para o Sistema CYGNUS: módulo Arbitro e Módulo Supervisor. O Módulo Arbitro possibilita que o computador trabalhe em configuração multiprocessadora, já que disciplina o uso da barra de comunicação comum (VME) entre os Módulos Processadores. O módulo Supervisor foi construído para dar suporte a uma série de funções de gerenciamento e supervisão do sistema como um todo, possibilitando um melhor entendimento de seu comportamento e, conseqüentemente, um melhor aproveitamento de seus recursos. / [en] The CYGNUS System is a Motorola MC86000 based shared memory multiprocessor, with a modular architecture, that is being developd by the Engenharia Elétrica and Informática Departaments of PUC/RJ. This work is concerned with the design and implementation of two CYGNUS modules: the Arbiter Module and the Supervisor Module. The Arbiter Module allows CYGNUS to work in a multiprocessor configuration, by determining which Processor Module will access the common bus (VMF Standard), and dealing with the bus cintention. The Supervisor Module is a special Procesor Module, built to give support to a set of system management and supervision functions, which will make possible a better understanding of the system´s behavior, and a rational utilization of its resources.

The advent of multi-core processors, particularly with projections that numbers of cores will continue to increase, has focused attention on parallel programming. It is widely recognized that current programming techniques, including those that are used for scientific parallel programming, will not allow the easy formulation of general purpose applications. An area which is receiving interest is the use of programming styles which do not have side-effects. Previous work on parallel functional programming demonstrated the potential of this to permit the easy exploitation of parallelism. This thesis investigates a dynamic load balancing system for shared memory Chip Multiprocessors. This system is based on a parallel computing model called SLAM (Spreading Load with Active Messages), which makes use of functional language evaluation techniques. A novel hardware/software mechanism for exploiting fine grain parallelism is presented. This mechanism comprises a runtime system which performs dynamic scheduling and synchronization automatically when executing parallel applications. Additionally the interface for using this mechanism is provided in the form of an API. The proposed system is evaluated using cycle-level models and multithreaded applications running in a full system simulation environment.

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International Telemetering Conference Proceedings / November 04-07, 1991 / Riviera Hotel and Convention Center, Las Vegas, Nevada / In this paper we describe the design of the REAL/STAR 2000 system, a highperformance real-time computer for telemetry applications. The REAL/STAR 2000 is a symmetric, tightly-coupled multiprocessor, optimized for real-time processing. The system provides a high level of scalability and flexibility by supporting three configurations: single, dual, and quad processor configurations, based on Motorola 88100 RISC processors. The system runs the multiprocessor REAL/IX operating system, a real-time implementation of the AT&T UNIX System V. It compiles with BCS and OCS standards, meets the POSIX 1003.1 standard, and has the current functionality of the emerging POSIX 1003.4 real-time standard. The REAL/STAR 2000 promotes an open system approach to real-time computing by supporting major industry standards. Benchmark results are also presented in the paper.