<p>In this thesis the models of Si-LDMOS transistors have been investigated with Agilent EEsof ADS version 2002a for operation in the 2-6 GHz frequency range. The first one is the Motorola’s (MRF21010) model based on a 30 mm prototype of a Si-LDMOS transistor. The second one is a model based on a 1 mm prototype of Si-LDMOS transistor developed at Chalmers University. Large-signal simulations of Chalmers’ model have demonstrated results, which lead to the conclusion that,this model cannot be efficiently utilised for design for a PA in the 2-6 GHz frequency range. However, additional simulations with reduced Rd (drain losses) show the deep impact of this parameter on the main properties of the designed PA. Hence, it is important to take it into account during new processes of Si-LDMOS as well as to improve the CAD model. The final conclusion regarding Si-LDMOS cannot be made just based on these simulation results, since they are not in accordance with the published ones. The next step should be aimed at improving the model and further investigation of Si-LDMOS to prove their ability to operate in the 2-6 GHz frequency range.</p>

Nous menons, dans le cadre de la grammaire générative chomskienne, une analyse formelle des énoncés ramifiés du langage naturel ( « La plupart des linguistes et la plupart des philosophes s'apprécient »). Ces énoncés présentent des quantificateurs non linéairement dépendants, qui doivent être traités « en parallèle », alors que leur ordre d'apparition en surface est nécessairement linéaire. Ce phénomène est connu en logique sous le nom de ramification (‘branching quantification') ; en grammaire générative il se traduit par des exigences contradictoires au niveau de la relation de c-commande : symétrie par l'absence de c-commande entre constituants quantifiés au niveau de la forme logique (‘LF') et antisymétrie par la relation de c commande asymétrique au niveau de la forme de surface (en acceptant l'axiome de correspondance linéaire ‘LCA' de Kayne). Pour sortir de cette impasse nous introduisons un nouveau type d'objets que nous avons nommés objets doubles. Les objets doubles créent localement des îlots non linéaires qui permettent d'obtenir la linéarité recherchée en surface sans induire de dépendance au niveau de la forme logique. Leur introduction est justifiée par ailleurs par le traitement qu'ils permettent de la coordination, un phénomène étroitement lié à la ramification. Grâce aux objets doubles tous les types de ramification, avec ou sans coordination, reçoivent une représentation adéquate, menant à une interprétation correcte. Nous résultats trouvent également une application en logique modale épistémique, et pour la représentation de l'interrogation multiple. / We carry out, within the framework of Chomskian generative grammar, a formal analysis of branching sentences in natural language (“Most linguists and most philosophers appreciate each other”). These sentences present quantifiers that are not linearly dependent, which must be treated "in parallel", whereas their surface order is necessarily linear. This phenomenon is known in logic as branching quantification. In generative grammar, branching quantification leads to contradictory requirements on the c-command relation: on the one hand, because of the absence of c-command between quantified constituents, one should have symmetry at LF; on the other hand, accepting Kayne's Linear Correspondence Axiom LCA, one should have antisymmetry of c-command at PF. To leave this dead end we introduce a new type of objects which we named twin objects (‘objets doubles' in French). Twin objects locally create nonlinear islands which make it possible to obtain the expected linearity at the surface without inducing dependence at the level of Logical Form. Their introduction is moreover justified by the treatment of coordination they allow, a phenomenon closely related to branching. Thanks to twin objects all types of branching, with or without coordination, receive an adequate representation, leading to a correct interpretation. Our results also find applications in epistemic modal logic and in the representation of multiple wh-questions.

In this thesis, design aspects of fully integrated multibandmultistandard front-end receivers are investigated based onthree fundamental aspects: noise, linearity and operatingfrequency. System level studies were carried out to investigatethe effects of different modulation techniques, duplexing andmultiple access methods on the noise, linearity and selectivityperformance of the circuit. Based on these studies and thelow-cost consideration, zero-IF, low-IF and wideband-IFreceiver architectures are promising architectures. These havea common circuit topology in a direct connection between theLNA and the mixer, which has been explored in this work toimprove the overall RF-to-IF linearity. One front-end circuitapproach is used to achieve a low-cost solution, leading to anew multiband multistandard front-end receiver architecture.This architecture needs a circuit whose performance isadaptable due to different requirements specified in differentstandards, works across several RF-bands and uses a minimumamount ofexternal components. Five new circuit topologies suitable for a front-endreceiver consisting of an LNA and mixer (low-noise converter orLNC) were developed. A dual-loop wide-band feedback techniquewas applied in all circuits investigated in this thesis. Threeof the circuits were implemented in 0.18 mm RF-CMOS and 25 GHzbipolar technologies. Measurement results of the circuitsconfirmed the correctness of the design approach. The circuits were measured in several RF-bands, i.e. in the900 MHz, 1.8 GHz and 2.4 GHz bands, with S11 ranging from–9.2 dB to–17 dB. The circuits have a typicalperformance of 18-20 dB RF-to-IF gain, 3.5-4 dB DSB NF and upto +4.5 dBm IIP3. In addition, the circuit performance can beadjusted by varying the circuit’s first-stage biascurrent. The circuits may work at frequencies higher than 3GHz, as only 1.5 dB of attenuation is found at 3 GHz and nopeaking is noticed. In the CMOS circuit, the extrapolated gainat 5 GHz is about 15 dB which is consistent with the simulationresult. The die-area of each of the circuits is less than 1mm2.

Advanced digital modulation schemes used in the wireless applications, result in the modulated RF signals with high peak to average power ratio which requires linear amplification. On the other hand, the demand for a longer talk time with less battery volume and weight, especially in hand-held radio units, necessitate more power efficient methods to be utilized in power amplifier design. But improved linearity and efficiency have always been contradicting requirements demanding innovative power amplifier and linearizer design techniques. Dynamically varying the load impedance and bias point of a transistor according to the varying envelope of the incoming RF signal also known as Dynamic Load Modulation (DLM) and Dynamic Supply Modulation (DSM), respectively, are two separate methods for improving the efficiency in power amplifier design. In this dissertation, a combination of both variable gate bias and tunable load concepts is applied in an amplifier structure consisting of two transistors in parallel. A novel computer aided design methodology is proposed for careful selection of the load and biasing points of the individual transistors. The method which is based on load-pull analysis performs sweeps on the gate bias voltages of the active devices and input drive level of the amplifier in order to obtain ranges of biases that result in the generation of IMD sweet spots. Following that, the amplifier is designed employing the load line theory and bias switching at the same time in order to enhance the efficiency in reduced drive levels while extending the output 1 dB compression point to higher values at higher drives. Tunable matching networks are implemented utilizing varactor stacks in a &Pi / con

Advanced digital modulation schemes used in the wireless applications, result in the modulated RF signals with high peak to average power ratio which requires linear amplification. On the other hand, the demand for a longer talk time with less battery volume and weight, especially in hand-held radio units, necessitate more power efficient methods to be utilized in power amplifier design. But improved linearity and efficiency have always been contradicting requirements demanding innovative power ampli

The implementation of highly integrated multi-bands and multi-standards reconfigurable radio transceivers is one of the great challenges in the area of integrated circuit technology today. In addition the rapid market growth and high quality demands that require cheaper and smaller solutions, the technical requirements for the transceiver function of a typical wireless device are considerably multi-dimensional. The major key performance metrics facing RFIC designers are power dissipation, speed, noise, linearity, gain, and efficiency. Beside the difficulty of the circuit design due to the trade-offs and correlations that exist between these parameters, the situation becomes more and more challenging when dealing with multi-standard radio systems on a single chip and applications with different requirements on the radio software and hardware aiming at highly flexible dynamic spectrum access. In this dissertation, different solutions are proposed to improve the linearity, reduce the noise and power consumption in analog and RF circuits and systems. A system level design digital approach is proposed to compensate the harmonic distortion components produced by transmitter circuits’ nonlinearities. The approach relies on polyphase multipath scheme uses digital baseband phase rotation pre-distortion aiming at increasing harmonic cancellation and power consumption reduction over other reported techniques. New low power design techniques to enhance the noise and linearity of the receiver front-end LNA are also presented. The two proposed LNAs are fully differential and have a common-gate capacitive cross-coupled topology. The proposed LNAs avoids the use of bulky inductors that leads to area and cost saving. Prototypes are implemented in IBM 90 nm CMOS technology for the two LNAs. The first LNA covers the frequency range of 100 MHz to 1.77 GHz consuming 2.8 mW from a 2 V supply. Measurements show a gain of 23 dB with a 3-dB bandwidth of 1.76 GHz. The minimum NF is 1.85 dB while the input return loss is greater than 10 dB across the entire band. The second LNA covers the frequency range of 100 MHz to 1.6 GHz. A 6 dBm third-order input intercept point, IIP3, is measured at the maximum gain frequency. The core consumes low power of 1.55 mW using a 1.8 V supply. The measured voltage gain is 15.5 dB with a 3-dB bandwidth of 1.6 GHz. The LNA has a minimum NF of 3 dB across the whole band while achieving an input return loss greater than 12 dB. Finally, A CMOS single supply operational transconductance amplifier (OTA) is reported. It has high power supply rejection capabilities over the entire gain bandwidth (GBW). The OTA is fabricated on the AMI 0.5 um CMOS process. Measurements show power supply rejection ratio (PSRR) of 120 dB till 10 KHz. At 10 MHz, PSRR is 40 dB. The high performance PSRR is achieved using a high impedance current source and two noise reduction techniques. The OTA offers a very low current consumption of 25 uA from a 3.3 V supply.

This thesis addresses the potential of implementing watt-level class-AB Power Amplifier (PA) for WLAN in 65 nm CMOS technology, at 2.4 GHz frequency. In total, five PAs have been compared, where the examined parameters were output power (Pout), linearity, power added efficiency (PAE), and area consumption. Four PAs were implemented using conventional cascode topology with different combination of transistors sizes in 65nm CMOS, and one PA using a high-voltage Extended Drain MOS (EDMOS) device, implemented in the same 65 nm CMOS with no process or mask changes. All schematics were created using Cadence Virtuoso CAD tools. The test benches were created using the Agilent's Advance Design System ( ADS) and simulated with the ADS-Cadence dynamic link. The simulation results show that the EDMOS PA (L=350 nm) has the smallest area, but has harder to reach the required Pout. Cascode no. 3 (L= 500,260 nm) has the best Pout (29.1 dBm) and PAE (49.5 %). Cascode no. 2 (L= 500,350 nm) has the best linearity (low EVM). Cascode no. 1 (L=500,500 nm) has low Pout (27.7 dBm). Cascode no.4 (L=500,60 nm) has very bad linearity. The thesis also gives an overview for CMOS technology, discusses the most important aspects in RF PAs design, such as Pout, PAE, gain, and matching networks. Different PA classes are also discussed in this thesis.

In this thesis the models of Si-LDMOS transistors have been investigated with Agilent EEsof ADS version 2002a for operation in the 2-6 GHz frequency range. The first one is the Motorola’s (MRF21010) model based on a 30 mm prototype of a Si-LDMOS transistor. The second one is a model based on a 1 mm prototype of Si-LDMOS transistor developed at Chalmers University. Large-signal simulations of Chalmers’ model have demonstrated results, which lead to the conclusion that,this model cannot be efficiently utilised for design for a PA in the 2-6 GHz frequency range. However, additional simulations with reduced Rd (drain losses) show the deep impact of this parameter on the main properties of the designed PA. Hence, it is important to take it into account during new processes of Si-LDMOS as well as to improve the CAD model. The final conclusion regarding Si-LDMOS cannot be made just based on these simulation results, since they are not in accordance with the published ones. The next step should be aimed at improving the model and further investigation of Si-LDMOS to prove their ability to operate in the 2-6 GHz frequency range.

High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption. An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth. Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power. High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels.

Certain nonlinear binary codes having at least twice as many codewords as any known linear binary code can be regarded as the binary images of linear codes over Z4. This vision leads to a new concept in coding theory, called the Z4-linearity of binary codes. This thesis is a survey on the linear quaternary codes and their binary images under the Gray map. The conditions for the binary image of a linear quaternary code to be linear are thoroughly investigated and the Z4-linearity of the Reed-Muller and Hamming codes is discussed. The contribution of this study is a simplification on the testing method of linearity conditions via a few new lemmas and propositions. Moreover, binary images (of length 8) of all linear quaternary codes of length 4 are analyzed and it is shown that all 184 binary codes in the nonlinear subset of these images are worse than the (8, 4) Hamming code. This thesis also includes the Hensel lift and Galois ring which are important tools for the study of quaternary cyclic codes. Accordingly, the quaternary cyclic versions of the well-known nonlinear binary codes such as the Kerdock and Preparata codes and their Z4-linearity are studied in detail.