Quantifying tissue volumes in pediatric brains from magnetic resonance (MR) images can provide insight into etiology and onset of neurological disease. Unbiased volumetric analysis can be applied to large population studies when automated image processing is possible. Standard segmentation strategies using adult atlases fail to account for varying tissue contrasts and types associated with the rapid growth and maturational changes seen in early neurodevelopment. The goal of this project was to develop an automated pipeline and two age-specific atlases capable of providing accurate tissue classification despite these challenges. The automated pipeline consisted of a stepwise initial atlas-to-subject registration, expectation maximization (EM) atlas based segmentation, and a post-processing level set segmentation for improved white/gray matter separation. This level set segmentation is a 3D and multiphase adaptation of a 2D method intended for use on images with the types of intensity Inhomogeneities found in MR images. The initial tissue maps required to determine spatial priors for the one-year-old atlas were created by manually cleaning the results of an adult atlas and the automated pipeline. Additional tissue maps were incrementally added until the spatial priors were sufficiently representative. The neonate atlas was similarly created, starting with the one-year-old atlas.

Nous abordons ici la thématique des opérateurs et processeurs flot de données dédiés au traitement d'images et orientés vers la morphologie mathématique. L'objectif principal est de proposer des architectures performantes capables de réaliser les opérations simples de ce corpus mathématique afin de proposer des opérateurs morphologiques avancés. Ces dernières années, des algorithmes astucieux ont été proposés avec comme objectif de réduire la quantité des calculs nécessaires à la réalisation de transformations telle que la ligne de partage des eaux. Toutefois, les mises en œuvre proposées font souvent appel à des structures de données complexes qui sont difficiles à employer sur des machines différentes des processeurs généralistes monocœurs. Les processeurs standard poursuivant aujourd'hui leur évolution vers une augmentation du parallélisme, ces implémentations ne nous permettent pas d'obtenir les gains de performance escomptés à chaque nouvelle génération de machine. Nous proposons alors des mises en œuvre rapides des opérations complexes de la morphologie mathématique par des machines exploitant fortement le parallélisme intrinsèque des opérations basiques. Nous étudions dans une première partie les processeurs de voisinage travaillant directement sur un flot de pixels et nous proposons différentes méthodologies de conception rapide de pipelines dédiés à une application. Nous proposons également une structure de pipeline programmable via l'utilisation de processeurs vectoriels avec différentes possibilités de chaînage. Enfin, une étude avec des machines est proposée afin d'observer la pertinence de notre approche.

<p>The purpose of this thesis is to construct a"Program Address Generator"(PAG) to a 24-bit Harvard type, RISC DSP processor using the VHDL language. The PAG is a part of the program control unit, and should consist of the following units: </p><p>A system stack for storing jump and loop information. A program counter, a status register, a stack pointer, an operating mode register and two registers called loop address and loop counter register, to support hardware loops. </p><p>The PAG handles the fetch stage of the processor pipeline, and should handle instructions such as the jump, subroutine jump, return from subroutine/interrupt and loop instructions, among others. </p><p>The PAG was successfully designed, and its function verified through extensive tests, where common combinations of ASM instructions were tested. Files for automated testing was created, to support easy testing if only small changes are applied to the PAG.</p>

<p>Digitizing objects and environments from real world has become an important part of creating realistic computer graphics. Through the use of structured lighting and laser time-of-flight measurements the capturing of geometric models is now a common process. The result are visualizations where viewers gain new possibilities for both visual and intellectual experiences. </p><p>This thesis presents the reconstruction of the Parthenon temple and its environment in Athens, Greece by using a 3D laser-scanning technique. </p><p>In order to reconstruct a realistic model using 3D scanning techniques there are various phases in which the acquired datasets have to be processed. The data has to be organized, registered and integrated in addition to pre and post processing. This thesis describes the development of a suitable and efficient data processing pipeline for the given data. </p><p>The approach differs from previous scanning projects considering digitizing this large scale object at very high resolution. In particular the issue managing and processing huge datasets is described. </p><p>Finally, the processing of the datasets in the different phases and the resulting 3D model of the Parthenon is presented and evaluated.</p>

Graduation date: 2006 / The design of a 10-bit pipelined charge redistribution DAC employing MOSCAPs biased in their accumulation mode is presented in this thesis. A switched capacitor filter and output buffer have also been designed for the system. The effect of MOSCAP nonlinearity on the performance of the pipelined charge redistribution DAC has been analyzed. MOS capacitors and their models available for simulation have been discussed. In addition, the effect of more general capacitor nonlinearities on the performance of the DAC has been presented.

<p><font face="Times New Roman"><font face="Times New Roman"> <p align="left">As a case study, the paper analyzes the Bank&rsquo / s role in the Chad-Cameroon Petroleum Development and Oil Pipeline project (the project) in which the Bank has been involved since the year 2000. The paper presents the lessons, challenges and implications from this protection of human rights.</p> </font></font></p>

This study has successfully identified transcripts differentially expressed in the salivary gland and midgut and provides candidate genes that are critical to response to parasite invasion. Furthermore, an open-source Glossina resource (G-ESTMAP) was developed that provides interactive features and browsing of functional genomics data for researchers working in the field of Trypanosomiasis on the African continent.

High-performance embedded networks are found in computer systems that perform applications such as radar signal processing and multimedia rendering. The system can be composed of multiple computer nodes that are interconnected with the network. Properties of the network such as latency and speed affect the performance of the entire system. A node´s access to the network is controlled by a medium access protocol. This protocol decides e.g. real-time properties and services that the network will offer its users, i.e. the nodes. Two such network protocols with heterogeneous real-time services are presented. The protocols offer different communication services and services for parallel and distributed real-time processing. The latter services include barrier synchronisation, global reduction and short message service. A network topology of a unidirectional pipelined optical fibre-ribbon ring is assumed for both presented protocols. In such a network several simultaneous transmissions in non-overlapping segments are possible. Both protocols are aimed for applications that require a high-performance embedded network such as radar signal processing and multimedia. In these applications the system can be organised as multiple interconnected computation nodes that co-operate in parallel to achieve higher performance. The computing performance of the whole system is greatly affected by the choice of network. Computing nodes in a system for radar signal processing should be tightly coupled, i.e., communications cost, such as latency, between nodes should be small. This is possible if a suitable network with an efficient protocol is used. The target applications have heterogeneous real-time requirements for communication in that different classes of data-traffic exist. The traffic can be classified according to its requirements. The proposed protocols partition data-traffic into three classes with distinctly different qualities. These classes are: traffic with hard real-time demands, such as mission critical commands; traffic with soft real-time demands, such as application data (a deadline miss here only leads to decreased performance); and traffic with no real-time constraints at all. The protocols are analysed and performance is tested through simulation with different data-traffic patterns.

The purpose of this thesis is to construct a"Program Address Generator"(PAG) to a 24-bit Harvard type, RISC DSP processor using the VHDL language. The PAG is a part of the program control unit, and should consist of the following units: A system stack for storing jump and loop information. A program counter, a status register, a stack pointer, an operating mode register and two registers called loop address and loop counter register, to support hardware loops. The PAG handles the fetch stage of the processor pipeline, and should handle instructions such as the jump, subroutine jump, return from subroutine/interrupt and loop instructions, among others. The PAG was successfully designed, and its function verified through extensive tests, where common combinations of ASM instructions were tested. Files for automated testing was created, to support easy testing if only small changes are applied to the PAG.

Exclusionary discipline policies (Casella, 2003; Christle, Jolivette & Nelson, 2005; Tuzzolo & Hewitt, 2007), academic failure and school dropout are some of the most salient factors in the school to prison pipeline (Christle, Jolivette & Nelson, 2005). While previous research has explored the variability in existing exclusionary discipline policies and identified numerous factors associated with expulsion or criminal justice outcomes among youth, there has been little effort to bring these individual and school level factors together into a single predictive model that is informed by existing criminological theories. In this context, the proposed study will use multiple waves of data from the National Longitudinal Study of Adolescent Health to consider how school discipline policies, demographics, and competing criminological explanations affect the risk of expulsion and then future contact with the criminal justice system. Findings reveal that school-level factors such as severe disciplinary policies, school size, and school type are weak predictors of expulsion and adult arrest. Conversely, measures of social bonding, low self-control, learning, and strain theories show promise in predicting expulsion and arrest outcomes. A history of school disciplinary actions and self-reported delinquency present themselves as the strongest predictors of expulsion and subsequent arrest. Theoretical and policy implications are considered.