随着无线通信的蓬勃发展，新的通信标准不断出现，频谱利用率和数据传输速率提高的同时，传输信号的带宽和均峰比也不断增加。此外，多种通信标准共存的现状要求收发机能够在多个载波频率，高效率地传输不同格式的信号。因此，宽带运行和高效的放大高均峰比信号成为了基站功率放大器设计的基本要求。 / Doherty 功率放大器结构简单，增加效率的同时能保持中等线性度，故而受到了广泛关注。本文囊括了三个有关增加Doherty 放大器工作带宽、延展高效率区或提高功率利用因子的创新设计。 / 第一个设计中，复数合路阻抗被用于扩宽Doherty 放大器的高效率区。关于动态阻抗范围，电流比因子和漏极效率的理论分析说明，复数合路阻抗可以当作新的自由度来增加放大器的高效率区。为了验证有关理论，以2GHz 为工作频点，我们使用了相同的基于GaN 工艺的晶体管，分别设计了使用复数合路阻抗和纯实数合路阻抗的Doherty 放大器。连续波测试结果显示，使用复数合路阻抗的Dohety 放大器能够提高9.1dB 的输出回退范围，比基于纯实数合路阻抗的传统设计要高3.6dB。此外，使用单载波、均峰比9.6dB 的WCDMA 信号的测试显示，基于复数合路阻抗的设计在输出功率为33.2dBm 时，其平均漏极效率高达57.4%。 / 第二个设计中使用了随频率变化的复数合路阻抗，通过控制漏极电流，来同时增加Doherty 放大器的工作带宽和高效率区。为了验证有关理论，我们设计了输出功率42dBm、工作带宽1.8-2.2GHz、输出回退区9dB 的Doherty 放大器。连续波测试结果显示，在8.5dB 回退点处，该设计在8.5dB 回退点和饱和输出点的漏极效率分别高达55-59%和69-73%。使用单载波、均峰比9.6dB 的WCDMA 信号的测试显示，该设计在输出功率为33.5dBm 时，其平均漏极效率高达53-58%，邻道抑制比也能保持在-30dBc。 / 最后一个设计中，一种在辅助支路加入变换器的Doherty 结构被用于宽带放大。理论分析显示了该结构能够增加功率利用因子，并提供宽带Doherty 特性。为了验证有关理论，我们设计了输出功率20W、工作带宽1.6-2.4GHz、功率利用因子得到改善的Doherty 放大器。连续波测试结果显示，该设计的功率利用因子高达0.94，所有频点均可得到良好的Doherty 效率特性，该设计在6dB回退点和饱和输出点的漏极效率分别高达55-64%和68-76%。在2GHz 处，使用单载波、均峰比6.6dB 的WCDMA 信号的测试显示，该设计在输出功率为37dBm时，其平均漏极效率高达56%，邻道抑制比低于-37dBc。 / As modern communication system demands higher spectrum efficiency and data rate, new communication standard using complex modulation scheme has emerged and led to transmitting signal with ever-increasing Peak-to-Average Power Ratio (PAPR). Moreover, the co-existence of different standards requires RF transceivers to support signal transmission at multiple carrier frequencies. Therefore, wideband operation and efficient amplification of high PAPR signal are prime requirements for base-station PA design. / For efficiency enhancement, the Doherty Power Amplifier (DPA) [1] has been regarded as the most popular approach due to its circuit simplicity and moderate linearity. Three innovative DPA design techniques relating to the enhancement of operating bandwidth, high efficiency range and power utilization factor (PUF) are proposed in this work. / In the first demonstration, a novel DPA configuration with Complex Combining Load (CCL) is presented to extend the high efficiency range of the amplifier. Theoretical analysis of dynamic load span, current ratio and drain efficiency reveals that complex combining load can offer a new degree of freedom to boost the Output Back-off (OBO) of DPA. For verification, a 2GHz, equal-cell, GaN HEMT-based DPA is simulated, prototyped and measured with both complex and resistive combining loads. Under Continuous Wave (CW) excitation, measurement results show that the CCL DPA can attain an OBO of 9.1 dB which is 3.6 dB higher than that of the RCL design. In addition, by the use of single-carrier WCDMA signal with PAPR of 9.6 dB and at an average output power of 33.2 dBm, the CCL design is found to deliver an average drain efficiency of 57.4%. / The second design presents a novel technique to extend the bandwidth and efficiency range of DPA by the adoption of frequency-varying Complex Combining Load and proper input current control strategy. For verification, a 42 dBm, 1.8-2.2 GHz DPA with OBO of 8.5 dB was designed, built and characterized. Under CW stimulation, a back-off efficiency (8.5 dB) of 55-59% and saturation efficiency of 69-73% were observed over the entire bandwidth. With single carrier WCDMA signal excitation (PAPR of 9.6 dB), an average drain efficiency of 53-58% was obtained at 33.5 dBm average output power and Adjacent Channel Leakage Power Ratio (ACLR) of around -30 dBc. / In the last technique, a novel DPA configuration with auxiliary transformer is presented for broadband operation. Theoretical analysis reveals that the presented design can offer enhanced PUF and wideband Doherty behavior. Based on the proposed theory, a 1.6-2.4 GHz, 20 W DPA with improved PUF is designed, simulated and measured. Under CW excitation, measurement results indicate that the presented DPA can achieve a PUF of 0.94, good Doherty behavior over the entire frequency band with a 6 dB back-off efficiency of 55-64% and saturated efficiency of 68-76%. In addition, by the use of single-carrier WCDMA signal (centered at 2 GHz) with PAPR of 6.6 dB and at an average output power of 37 dBm, an average drain efficiency of 56% is obtained with ACLR of better than -37 dBc. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Fang, Xiaohu. / Thesis (Ph.D.) Chinese University of Hong Kong, 2015. / Includes bibliographical references. / Abstracts also in Chinese.

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Chan Kwok-po. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter Chapter 2 --- Characterization of Nonlinearity in Power Amplifier --- p.6 / Chapter 2.1. --- Ideal Amplifier Representation --- p.6 / Chapter 2.2. --- Nonlinear Amplifier Representation --- p.7 / Chapter 2.2.1 --- Series Representation --- p.7 / Chapter 2.2.2 --- AM-AM and AM-PM Distortion --- p.7 / Chapter 2.2.3 --- Two-tone Intermodulation --- p.9 / Chapter 2.2.4 --- Nonlinearity on Digital Modulation Formats --- p.11 / Chapter Chapter 3 --- Linearization Techniques --- p.13 / Chapter 3.1. --- Power Back-off --- p.14 / Chapter 3.2. --- Feedback Technique --- p.15 / Chapter 3.3. --- Pre-distortion Technique --- p.16 / Chapter 3.4. --- Feed-forward Technique --- p.18 / Chapter 3.5. --- Linearization Systems with Signal Processing --- p.19 / Chapter 3.5.1 --- Envelope Elimination and Restoration (EER) --- p.19 / Chapter 3.5.2 --- Linear Amplification Using Nonlinear Components (LINC) --- p.20 / Chapter 3.5.3 --- Combined Analogue-locked Loop Universal Modulator (CALLUM) --- p.21 / Chapter 3.5.4 --- Linear Amplification Employing Sampling Techniques (LIST) --- p.21 / Chapter 3.6. --- Other Linearization Techniques --- p.22 / Chapter Chapter 4 --- Feed-forward Power Amplifier System --- p.23 / Chapter 4.1. --- General Description --- p.23 / Chapter 4.2. --- Adaptive Feed-forward Power Amplifier System --- p.25 / Chapter 4.2.1 --- Power Minimization --- p.28 / Chapter 4.2.2 --- Pilot Injection Technique --- p.29 / Chapter 4.2.3 --- Look-up-table Technique (Temperature Compensation) --- p.31 / Chapter 4.2.4 --- Correlation Based Feedback Control (Dual-loop) --- p.32 / Chapter 4.2.5 --- Correlation Based Feedback Control (Triple-loop) --- p.34 / Chapter 4.2.6 --- Digital Implementation on Adaptive FFPA --- p.35 / Chapter Chapter 5 --- DSP-based Adaptive FFPA Analysis --- p.37 / Chapter 5.1. --- System Architecture --- p.37 / Chapter 5.2. --- System Modeling --- p.39 / Chapter 5.3. --- Principle of Adaptation --- p.40 / Chapter 5.3.1 --- Adaptation in Error Extraction Loop --- p.40 / Chapter 5.3.2 --- Adaptation in Main-tone Suppression Loop --- p.43 / Chapter 5.3.3 --- Adaptation in Distortion Cancellation Loop --- p.44 / Chapter 5.3.4 --- Complex Adaptation --- p.46 / Chapter 5.4. --- Adaptation Performance Analysis --- p.47 / Chapter 5.4.1 --- Condition for Convergence --- p.47 / Chapter 5.4.2 --- Rate of Convergence --- p.48 / Chapter 5.4.3 --- Misadjustment --- p.49 / Chapter 5.4.4 --- Summary of the System Performance --- p.51 / Chapter 5.5. --- System Design Consideration --- p.51 / Chapter 5.5.1 --- Quadrature Sampling --- p.51 / Chapter 5.5.2 --- Data Processing --- p.52 / Chapter 5.6. --- Sensitivity Analysis --- p.55 / Chapter 5.6.1 --- Vector Representation --- p.55 / Chapter 5.6.2 --- Amplitude and Phase Matching --- p.56 / Chapter 5.6.3 --- Time-delay Matching --- p.58 / Chapter 5.7. --- Analog-to-digital Interface: Design Consideration --- p.60 / Chapter 5.7.1 --- Sampling Rate Consideration --- p.60 / Chapter 5.7.2 --- Finite Word-length --- p.61 / Chapter 5.8. --- Digital-to-analog Interface: Design Consideration --- p.63 / Chapter Chapter 6 --- New DSP Algorithms for High Performance Adaptive FFPA --- p.67 / Chapter 6.1. --- Variable Loop-gain Algorithm --- p.67 / Chapter 6.2. --- Variable Step-size Algorithm --- p.71 / Chapter 6.3. --- Least-mean-fourth Algorithm --- p.74 / Chapter Chapter 7 --- Implementation of DSP-based Adaptive FFPA --- p.79 / Chapter 7.1. --- Hardware Construction --- p.79 / Chapter 7.2. --- Experimental Results: LMS Algorithm --- p.82 / Chapter 7.3. --- Experimental Results: Variable Loop-gain Algorithm --- p.86 / Chapter 7.4. --- Experimental Results: Variable Step-size Algorithm --- p.88 / Chapter 7.5. --- Experimental Results: Lesat-mean-fourth Algorithm --- p.90 / Chapter Chapter 8 --- Conclusion --- p.92 / Appendix I Matlab Program for Computer Simulation of Adaptive FFPA --- p.A-l / Appendix II DSP Program for Experimental Adaptive FFPA --- p.A-5 / References --- p.R-1 / Author's Publications --- p.AP-1

No description available.

No description available.

Thesis (MTech(Electrical Engineering))--Cape Peninsula University of Technology, 2006. / Electronic communication systems have become an integral part of our everyday lives. RF (Radio Frequency) power amplifiers form part of the fundamental building blocks of an electronic communication system. RF power amplifiers can also be one of the major causes of distortion in an electronic communication system. This thesis describes the linearity requirement for a RF power amplifier that is used in a transmitter section of an electronic communication system. Furthermore, five different linearisation techniques are presented and their characteristics compared. Since a power amplifier employing the Feedforward linearisation technique was designed, built and tested, this thesis focuses on the Feedforward technique. The design methods for the various Feedforward components are presented. The measured parameters of the Feedforward linearised amplifier are compared with the measured parameters of a non-linearised amplifier.

Ng, Yuen Sum. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references. / Abstract also in Chinese. / Chapter 1. --- INTRODUCTION --- p.11 / Chapter 1.1 --- Motivation --- p.11 / Chapter 1.2 --- Specifications --- p.12 / Chapter 1.3 --- Organization of the Thesis --- p.16 / Chapter 1.4 --- References --- p.16 / Chapter 2. --- BASIC THEORY OF POWER AMPLIFIER AND TRANSMITTER FRONT-END --- p.18 / Chapter 2.1 --- Classification of Power Amplifier --- p.18 / Chapter 2.1.1 --- Class A --- p.20 / Chapter 2.1.2 --- Class B --- p.21 / Chapter 2.1.3 --- Class AB --- p.22 / Chapter 2.1.4 --- Class C --- p.23 / Chapter 2.1.5 --- Class D --- p.24 / Chapter 2.1.6 --- Class E --- p.25 / Chapter 2.1.7 --- Class F --- p.28 / Chapter 2.2 --- Figure-of-Mhrit of Power Amplifier --- p.28 / Chapter 2.2.1 --- Small Signal Analysis --- p.29 / Chapter 2.2.1.1 --- S-parameter --- p.29 / Chapter 2.2.1.2 --- Gain and Stability --- p.29 / Chapter 2.2.2 --- Large Signal Analysis --- p.32 / Chapter 2.2.2.1 --- 1-dB compression point --- p.33 / Chapter 2.2.2.2 --- Third-order intermodulation point --- p.33 / Chapter 2.2.2.3 --- Power Gain --- p.35 / Chapter 2.2.2.4 --- Drain Efficiency and Power Added Efficiency --- p.35 / Chapter 2.2.2.5 --- AM-AM and AM-PM conversion --- p.36 / Chapter 2.2.3 --- Modulation Analysis --- p.36 / Chapter 2.2.3.1 --- Constellation Diagram and Error Vector Magnitude --- p.36 / Chapter 2.3 --- Reference --- p.37 / Chapter 3. --- CIRCUIT DESIGN OF POWER AMPLIFIER --- p.39 / Chapter 3.1 --- Introduction --- p.39 / Chapter 3.2 --- Topology of the Power Amplifier Design --- p.39 / Chapter 3.3 --- Design in Power Amplifier --- p.40 / Chapter 3.2.1 --- Power Stage --- p.40 / Chapter 3.2.2 --- Driver Stage and Input matching --- p.46 / Chapter 3.4 --- Simulation Result on Power Amplifier --- p.49 / Chapter 3.5 --- Layout consideration --- p.50 / Chapter 3.6 --- Measurement Result on Power Amplifier --- p.51 / Chapter 3.4.1 --- Small signal measurement --- p.52 / Chapter 3.4.2 --- Large signal measurement --- p.55 / Chapter 3.4.3 --- Modulation measurement --- p.56 / Chapter 3.7 --- Performance Summary --- p.58 / Chapter 3.8 --- Reference --- p.59 / Chapter 4. --- CIRCUIT DESIGN OF TRANSMITTER FRONT-END --- p.60 / Chapter 4.1 --- Introduction --- p.60 / Chapter 4.2 --- Topology of the Transmitter Front-End Design --- p.61 / Chapter 4.3 --- Design in transmitter front-end circuit --- p.64 / Chapter 4.2.1 --- I/Q Modulator --- p.64 / Chapter 4.2.2 --- Power Amplifier --- p.66 / Chapter 4.2.3 --- On-chip LC Balun --- p.72 / Chapter 4.4 --- Simulation Result of the Transmitter Front-End Design --- p.74 / Chapter 4.5 --- Layout consideration --- p.75 / Chapter 4.6 --- Measurement Result of the Transmitter Front-End Design --- p.76 / Chapter 4.4.1. --- Transmitter Front-End Measurement --- p.77 / Chapter 4.4.1.1 --- Output Reflection coefficient --- p.77 / Chapter 4.4.1.2 --- Large Signal Measurement --- p.78 / Chapter 4.4.1.3 --- Modulation Measurement --- p.81 / Chapter 4.4.2. --- LC Balun Measurement --- p.84 / Chapter 4.7 --- Performance Summary of the transmitter front-end circuit --- p.86 / Chapter 4.8 --- Reference --- p.89 / Chapter 5. --- CONCLUSION --- p.90 / Chapter 6. --- FUTURE WORK --- p.91

The nonlinearity of RF power amplifiers (PA) is one of critical concerns for RF designers because it causes spectral regrowth related to in-band and out-of-band spurious emissions control in communication standards. Traditionally, RF power amplifiers must be backed off considerably from the peak of their power level in order to prevent spectral regrowth. The digital predistortion (DPD) technique is being widely used for compensation of the nonlinearity of RF power amplifiers, as the high power efficiency becomes increasely important in wireless communication systems. However, the latest generations of communication systems, such as Wi-Fi, WiMAX, and LTE, using wider bandwidth have some additional memory distortion, other than the traditional memoryless distortion. The distortion caused by memory effect makes the traditional predistorter not precise any more for the PA linearization. In this dissertation, the traditional prediction of 3rd order memoryless spectrum regrowth is applied to 4G communication signals in terms of the 3rd intercept point of PAs, based on the previous researches in Portland State University led by Professor Fu Li. Then, the spectrum regrowth prediction is extended to an arbitrarily high order with intercept points of an RF power amplifier. A simple predistortion method which enables direct calculation of the predistorter coefficients from the intercept points is also proposed. Furthermore, the memory effect is taken into account for both PA modeling and predistortion. A simplified Hammerstein structure based method is proposed to analyze the nonlinear characteristic of PAs more precisely and completely. By applying the inverse structures of the PA model, the proposed predistorter corrects both the traditional memoryless nonlinear distortions and the memory effect that may exist in RF power amplifiers. The order of nonlinearity and depth of memory of a predistorter can be chosen from 0 to any arbitrarily high number. This increases the flexibility for designers to decide how to linearize power amplifier effectively and efficiently.

This thesis is concerned with the design and implementation of radio frequency (RF) power amplifiers and micro-electromechanical systems---namely MEMS varactors. This is driven by the many wireless communication systems which are constantly moving towards increased integration, better signal quality, and longer battery life. / The power amplifier consumes most of the power in a receiver/transmitter system (transceiver), and its output signal is directly transmitted by the antenna without further modification. Thus, optimizing the PA for low power consumption, increased linearity, and compact integration is highly desirable. / Micro-electromechanical systems enable new levels of performance in radio-frequency integrated circuits, which are not readily available via conventional IC technologies. They are good candidates to replace lossy, low Q-factor off-chip components, which have traditionally been used to implement matching networks or output resonator tanks in class AB, class F, or class E power amplifiers. The MEMS technologies also make possible the use of new architectures, with the possibility of flexible re-configurability and tunability for multi-band and/or multi-standard applications. / The major effort of this thesis is focused on the design and fabrication of an RF frequency class AB power amplifier in the SiGe BiCMOS 5HP technology, with the capability of being tuned with external MEMS varactors. The latter necessitated the exploration of wide-tuning range MEMS variable capacitors, with prototypes designed and fabricated in the Metal-MUMPS process. / An attempt is made to integrate the power amplifier chip and the MEMS die in the same package to provide active tuning of the power amplifier matching network, in order to keep the efficiency of the PA constant for different input power levels and load conditions. / Detailed simulation and measurement results for all circuits and MEMS devices are reported and discussed.

This manuscript describes the design, development, and implementation of a linear high efficiency power amplifier. The symmetrical Doherty power amplifier utilizes TriQuint's 2nd Generation Gallium Nitride (GaN) on Silicon Carbide (SiC) High Electron Mobility Transistor (HEMT) devices (T1G6001032-SM) for a specified design frequency of 3.6 GHz and saturated output power of 40 dBm. Advanced Design Systems (ADS) simulation software, in conjunction with Modelithic's active and passive device models, were used during the design process and will be evaluated against the final measured results. The use of these device models demonstrate a successful first-pass design, putting less dependence on classical load pull analysis, thereby decreasing the design-cycle time. The Doherty power amplifier is a load modulated amplifier containing two individual amplifiers and a combiner network which provides an impedance inversion on the path between the two amplifiers. The carrier amplifier is biased for Class-AB operation and works as a conventional linear amplifier. The second amplifier is biased for Class-C operation, and acts as the peaking amplifier that turns on after a certain instantaneous power has been reached. When this power transition is met the carrier amplifier's drain voltage is already approaching saturation. If the input power is further increased, the peaking amplifier modulates the load seen by the carrier amplifier, such that the output power can increase while maintaining a constant drain voltage on the carrier amplifier. The Doherty power amplifier can improve the efficiency of a power amplifier when the input power is backed-off, making this architecture particularly attractive for high peak-to-average ratio (PAR) environments. The design presented in this manuscript is tuned to achieve maximum linearity at the compromise of the 6dB back-off efficiency in order to maintain a carrier-to- intermodulation ratio greater than 30 dB under a two-tone intermodulation distortion test with 5 MHz tone spacing. Other key figures of merit (FOM) used to evaluate the performance of this design include the power added efficiency (PAE), transducer power gain, scattering parameters, and stability. The final design is tested with a 20 MHz LTE waveform without digital pre-distortion (DPD) to evaluate its linearity reported by its adjacent channel leakage ratio (ACLR). The dielectric substrate selected for this design is 15 mil Taconic RF35A2 and was selected based on its low losses and performance at microwave frequencies. The dielectric substrate and printed circuit board (PCB) design were also modeled using ADS simulation software, to accurately predict the performance of the Doherty power amplifier. The PCB layout was designed so that it can be mounted to an existing 4" x 4" aluminum heat sink to dissipate the heat generated by the transistors while the part is being driven. The performance of the 3.6 GHz symmetrical Doherty power amplifier was measured in the lab and reported a maximum PAE of 55.1%, and a PAE of 48.5% with the input power backed-off by 6dB. These measured results closely match those reported by design simulations and demonstrate the models' effectiveness for creating a first-pass functional design.