Thèse de doctorat : Physique : Tours : 2008. / Titre provenant de l'écran-titre.

Thesis (Ph. D. in Physics)--Vanderbilt University, 2003. / Title from PDF title screen. Includes bibliographical references.

The present investigation focuses on the development of computationally efficient path planning algorithms for autonomous ground vehicles. The approach selected is based on a heuristic hill climbing local search. The cost index employed incorporates a traversability cost average, which offers two primary benefits: 1) the average extends the region of knowledge of the search algorithm, increasing optimality of the solution; and 2) the avoidance of hazardous regions is added to the decision making process. A binary traversability map representation is first utilized to analyze the performance of the enhanced heuristic hill climbing algorithm in comparison to the more traditional techniques. Next, the search algorithm is applied to a multi-valued traversability map to test the capabilities of the algorithm over natural terrain. For this purpose, a digital elevation map is automatically processed to obtain multi-valued traversability values through the de nition of a roughness, inclination and step index. The complete path planning architecture for natural terrain then consists of a three step approach, computation of the multi-valued traversability map, implementation of the enhanced heuristic hill climbing search algorithm, and a path relaxation step. This last step is employed to fine-tune and smooth the trajectory, eliminating sharp turns caused by the regular characteristics of the search space. / text

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Stress induced void formation in Cu interconnects, due to thermal stresses generated during the processing of semiconductors, is an increasing reliability issue in the semiconductor industry as Cu interconnects are being downscaled to follow the demand for faster chip speed. In this work, 1.8 micron and 180 nm wide Cu interconnects, fabricated by Freescale Semiconductors, were subjected to thermal cycles, in-situ in the TEM, to investigate the stress relaxation mechanisms as a function of interconnect linewidth. The experiments show that the 1.8 micron Cu interconnect lines relax the thermal stresses through dislocation nucleation and motion while the Cu interconnect 180 nm lines exhibit void formation. Void formation in 180 nm lines occurs predominantly at triple junctions where the Ta diffusion barrier meets a Cu grain boundary. In order to understand void formation in 180 nm lines, the grain orientation and local stresses are determined. In particular, Nanobeam Diffraction (NBD) in the TEM is used to obtain the diffraction pattern of each grain, from which the crystal orientation is evaluated by the ACT (Automated Crystallography for TEM) software. In addition, 2D Finite Element Method (FEM) simulations are performed using the Object Oriented Finite Modeling (OOF2) software to correlate grain orientation with local stresses, and consequently void formation. According to the experimental and simulation results obtained, void formation in 180nm Cu interconnects does not seem to be solely dependent on local stresses, but a combination of diffusion paths available, stress gradients and possibly the presence of defects. In addition, based on the in-situ TEM observations, void growth seems to occur through grain boundary and/or interfacial diffusion. However, in-situ STEM observations of fully opened voids post-failure show pileup of material at the Cu grain surfaces. This means that surface or interface diffusion is also very active during void growth in the presence of thermal stresses.

This thesis is mainly concerned with problems in the areas of the Calculus of Variations and Partial Differential Equations (PDEs). The properties of the functional to minimize with respect to the given topology play an important role in the existence of minimizers of integral problems. We will introduce the important concepts of quasiconvexity and polyconvexity. Inspired by finite element methods from Numerical Analysis, we introduce a perturbed problem which has some surprising uniqueness properties.

No description available.

Electron transport in vacuum deposited a-Se films has been investigated by Interrupted-Field Time-of-Flight (IFTOF) transient photoconductivity experiments to examine the effect of sample temperature (T) and applied electric field (F) on X-ray induced changes in the electron lifetime. Upon exposure to x-rays, the electron lifetime decreases. The decrease in normalized lifetime is almost linearly proportional to the absorbed dose, and is more significant at higher temperatures. Upon the cessation of x-ray irradiation, the lifetime recovers towards its equilibrium value through a structural relaxation process, and is characterized by a structural relaxation time. The structural relaxation time decreases with temperature in an Arrhenius fashion, and exhibits an activation energy that is roughly 1.4 eV. The structural relaxation time at room temperature (21 C) is 2 – 4 hrs whereas at 35 C, 6 – 10 mins. These measurements are important in characterizing the charge collection efficiency of a-Se based x-ray detectors, and its dependence on x-ray exposure and temperature. The results indicate that the rate of change of electron lifetime per unit exposure is less than 2%/Gy.

No description available.

With the advances in process technology, comes the domination of interconnect in the overall propagation delay in modern VLSI designs. Hence, interconnect synthesis techniques, such as buffer insertion, wire sizing and layer assignment play critical roles in the successful timing closure for EDA tools. In this thesis, while our aim is to satisfy timing constraints, accounting for the overhead caused by these optimization techniques is of another primary concern. We utilized a Lagrangian relaxation method to minimize the usage of buffers and metal resources to meet the timing constraints. Compared with the previous work that extended traditional Van Ginneken’s algorithm, which allows for bumping up the wire from thin to thick given significant delay improvement, our approach achieved around 25% reduction in buffer + wire capacitance under the same timing budget.