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Made available in DSpace on 2014-12-17T14:55:47Z (GMT). No. of bitstreams: 1 RafaelNAP_DISSERT.pdf: 1349793 bytes, checksum: 6843077c7952b1e58788ef395d9822e6 (MD5) Previous issue date: 2011-02-22 / This work proposes hardware architecture, VHDL described, developed to embedded Artificial Neural Network (ANN), Multilayer Perceptron (MLP). The present work idealizes that, in this architecture, ANN applications could easily embed several different topologies of MLP network industrial field. The MLP topology in which the architecture can be configured is defined by a simple and specifically data input (instructions) that determines the layers and Perceptron quantity of the network. In order to set several MLP topologies, many components (datapath) and a controller were developed to execute these instructions. Thus, an user defines a group of previously known instructions which determine ANN characteristics. The system will guarantee the MLP execution through the neural processors (Perceptrons), the components of datapath and the controller that were developed. In other way, the biases and the weights must be static, the ANN that will be embedded must had been trained previously, in off-line way. The knowledge of system internal characteristics and the VHDL language by the user are not needed. The reconfigurable FPGA device was used to implement, simulate and test all the system, allowing application in several real daily problems / Prop?e uma arquitetura em hardware, descrita em VHDL, desenvolvida para embarque de redes neurais artificiais, do tipo Multilayer Perceptron (MLP). Idealiza que, nessa arquitetura, as aplica??es com RNA tenham facilidade no procedimento de embarque de uma rede neural MLP em hardware, bem como permitam f?cil configura??o de v?rios tipos de redes MLP em campo, com diferentes topologias (quantidade de neur?nios e camadas). Uma rede de comunica??o foi desenvolvida para fazer reuso de neur?nios artificiais. A defini??o da arquitetura MLP que o sistema proposto ir? se configurar e executar depende de uma entrada de dados espec?fica, a qual define a quantidade de neur?nios, camadas e tipos de fun??es de ativa??o em cada neur?nio. Para permitir essa maleabilidade de configura??es nas RNA, um conjunto de componentes digitais (datapath) e um controlador foram desenvolvidos para executar instru??es que definir?o a arquitetura da rede MLP. Desta forma, o hardware funcionar? a partir de uma entrada de instru??es previamente conhecidas por um usu?rio, as quais indicar?o as caracter?sticas de uma determinada rede MLP, e o sistema ir? garantir a execu??o da MLP desejada a partir dos neur?nios artificiais desenvolvidos para o sistema, pelo controlador e pelos componentes do datapath, a rede de comunica??o interligar? os neur?nios e auxilia no reuso dos mesmos. Separadamente, os pesos e bias ter?o de estar fixos, ou seja, a rede neural a ser embarcada j? deve estar treinada de maneira off-line (realizada antecipadamente em software). A arquitetura vislumbra que o operador n?o necessite conhecer o dispositivo internamente, nem tampouco ter conhecimento sobre linguagem VHDL. O dispositivo reconfigur?vel e de prototipagem r?pida FPGA foi escolhido para implementa??o, simula??o e testes oportunizando aplicar o sistema a problemas reais do nosso cotidiano

RISC-V is growing in popularity as a free and open RISC Instruction Set Architecture (ISA) in academia and research. Also, the openness, simplicity, extensibility, and modularity, among its advantages, make it more and more used by designers in industry. The aim of this thesis is to design an open-source RISC-V processor. The development of this RISC-V processor was based on the prototype which was made in the course IL2232 Embedded Systems Design Project (SoI-CMOS Design group), against an experimental high-temperature SoC CMOS process. SystemVerilog was used for RTL coding. ModelSim was used for RTL simulation. Genus was used for digital synthesis and Innovus was used for digital place & route. The thesis concludes that this RISC-V processor can run the compiled C-code which has been produced by the virtual platform tool Imperas OVP. The instruction set RV32IM is the Instruction Set base for this processor. Through simulation, the CPI of this RISC-V processor can be collected while running different benchmark programs developed in two parallel Master thesis to this one. To a certain extent, it can reflect the performance of the processor. However, the actual execution time needs to be tested by loading the processor to the hardware. This part will not be discussed in this thesis but is left for future work. The gate count is collected by digital synthesis and the corresponding area is collected after digital place & route. / RISC-V växer i popularitet som en gratis och öppen RISC ISA inom akademi och forskning. Öppenheten, enkelheten, utbyggbarheten och modulariteten, bland dess fördelar, gör att den används mer och mer av designers inom industrin. Syftet med denna avhandling är att designa en RISC-V-processor med öppen källkod. Utvecklingen av denna RISC-V-processor baserades på prototypen som gjordes i kursen IL2232 Embedded Systems Design Project (SoI-CMOS Design group). Mot en experimentell högtemperatur, SoC CMOS-process diskuteras. SystemVerilog användes för RTL-kodning. ModelSim användes för RTL-simulering. Genus användes för digital syntes och Innovus användes för digital plats & rutt. Avhandlingen drar slutsatsen att denna RISC-V-processor kan köra den kompilerade C-koden som har producerats av det virtuella plattformsverktyget Imperas OVP. Instruktionsuppsättningen RV32IM är instruktionsuppsättningens bas för denna processor. Genom simulering kan CPI för denna RISC-V-processor samlas in samtidigt som man kör olika benchmarkprogram utvecklade i två parallella masteruppsatser till denna. Till viss del kan det spegla processorns prestanda. Den faktiska exekveringstiden måste dock testas genom att ladda processorn till hårdvaran. Denna del kommer att diskuteras i denna uppsats men lämnas för framtida arbete. Grindräkningen samlas in genom digital syntes och motsvarande yta samlas in efter den digitala platsen & rutten.

Ce mémoire porte sur la conception de l'interface numérique s'occupant, lors de la réception au sein d'un système de transmission de données, des problèmes d'accès au canal dans les protocoles large bande de type W-CDMA (Wideband Code Division Multiple Access / Multiplexage à large bande par code). Le cœur de la problématique se situe dans la partie numérique en bande de base, le récepteur RAKE. Ce récepteur est responsable de la démodulation du signal et de l'exploitation de la diversité du signal en identifiant et combinant les composantes de trajets multiples d'un même signal. En effet, cette dernière fonction est particulièrement importante d’une part de son rôle pour contrer les effets d'évanouissement causés par les trajets multiples, et d’autre part du rôle central du récepteur RAKE. La conception et l'implantation de celui-ci revêtent un caractère primordial. Dans ce mémoire, nous proposons une nouvelle architecture pour le récepteur RAKE : CodeRAKE. Les caractéristiques architecturales principales recherchées sont une grande flexibilité et une extensibilité aisée, tout en préservant la fonctionnalité et un bon équilibre entre ressources utilisées (et donc surface consommée) et performances (vitesse de fonctionnement). Pour satisfaire les contraintes de flexibilité et d'extensibilité, l'architecture CodeRAKE est partitionnée (pour être modulaire) en fonction du nombre d'utilisateurs et du nombre de codes par utilisateur, sans perdre de vue les contraintes de limitions de ressources utilisées et de préservation des performances. La modularité élevée de CodeRAKE permet l'application aisée de techniques de parallélisation permettant d'augmenter facilement les performances pour satisfaire notamment les besoins du côté de la station de base. L'approche architecturale mise en œuvre est souple et peut être facilement adaptée à d'autres protocoles existants ou futurs. Elle répond ainsi au défi des années à venir, où les récepteurs devront être capables de supporter de multiples protocoles et interfaces d'accès, notamment sous le contrôle de couches logicielles / This thesis focuses on the design of the air interface of W-CDMA (Wideband Code Division Multiple Access) systems, particularly on the aspects related to the channel access problems at the reception side. The main concern herein is the design of the baseband digital parts, that is, the RAKE receiver. This receiver is in charge of the signal demodulation and responsible for making profit of signal diversity. This late functionality is particularly important as it allows to counter signal fading by detecting and combining multipath components (leading to signal reinforcement) Given the central role of the RAKE receiver, its design and implementation are of paramount importance. In this thesis, we propose a new architecture for the RAKE receiver: CodeRAKE. The main architectural characteristics being aimed are high flexibility and scalability, yet preserving a good trade-off between resource use (and hence, area consumption) and performance (operation speed). In order to satisfy the flexibility and scalability constraints, the CodeRAKE architecture is modular and partitioned according to the number of users and the number of codes per user, with the resource limitation and performance preservation constraints in mind. The high levels of modularity of the CodeRAKE architecture allow an easy use of parallelisation techniques, which in turn allow an easy increase of performances, particularly at the base station side.The architectural approach proposed herein are versatile and can be easily adapted to other existing or future protocols. It responds to the challenge of the coming years, where the receiver will have to support multiple protocols and access interfaces, including control software layers

Les systèmes de communication modernes exigent des débits de plus en plus élevés afin de traiter des volumes d'informations en augmentation constante. Ils doivent être flexibles pour pouvoir gérer des environnements multinormes, et évolutifs pour s'adapter aux normes futures. Pour ces systèmes, la qualité du service (QoS) doit être garantie malgré l'évolution des technologies microélectroniques qui augmente la sensibilité des circuits intégrés aux perturbations externes (impact de particules, perte de l'intégrité du signal, etc.). La tolérance aux fautes devient un critère important pour améliorer la fiabilité et par conséquence la qualité de service. Cette thèse s'inscrit dans la continuité des travaux menés au sein du laboratoire LICM concernant la conception architecturale d'une chaîne de transmission à haut débit, faible coût, et sûre de fonctionnement. Elle porte sur deux axes de recherche principaux : le premier axe porte sur les aspects rapidité et flexibilité, et en particulier sur l'étude et l'implantation d'architectures parallèles-pipelines dédiées aux codeurs convolutifs récursifs. Le principe repose sur l'optimisation des blocs calculant le reste de la division polynomiale qui constitue l'opération critique du codage. Cette approche est généralisée aux filtres récursifs RII. Les caractéristiques architecturales principales recherchées sont une grande flexibilité et une extensibilité aisée, tout en préservant la fonctionnalité ainsi qu'un bon équilibre entre quantité de ressources utilisées (et donc surface consommée) et performances obtenues (vitesse de fonctionnement) ; le deuxième axe de recherche porte sur le développement d'une méthodologie de conception de codeurs sûrs en présence de fautes, améliorant ainsi la tolérance de circuits intégrés numériques. L’approche proposée consiste à ajouter aux codeurs des blocs supplémentaires permettant la détection matérielle en ligne de l'erreur afin d'obtenir des architectures sûrs en présence des fautes. Les solutions proposées permettent d'obtenir un bon compromis entre complexité et fréquence de fonctionnement. Afin d'améliorer encore le débit du fonctionnement, nous proposons également des versions parallèles-pipelines des codeurs sûrs. Différents campagnes d'injection de fautes simples, doubles, et aléatoires ont été réalisées sur les codeurs afin d'évaluer les taux de détection d’erreurs. L'étude architectures sûrs de fonctionnement a ensuite été étendue aux décodeurs parallèles-pipeline pour les codes cycliques en blocs. L'approche choisie repose sur une légère modification des architectures parallèles-pipeline développées / Nowadays, modern communication systems require higher and higher data throughputs to transmit increasing volumes of data. They must be flexible to handle multi-norms environments, and progressive to accommodate future norms. For these systems, quality of service (QoS) must be guaranteed despite the evolution of microelectronics technologies that increase the sensitivity of integrated circuits to external perturbations (impact of particles, loss of signal integrity, etc). Fault-tolerance techniques are becoming more and more an important criteria to improve the dependability and the quality of service. This thesis’work continues previous research undertaken at the LICM laboratory on the architectural design of high-speed, low-cost, and dependable transmission systems. It focuses on two principal areas of research : The first research area concerns the speed and flexibility aspects, particularly on the study and implementation of parallel-pipelined architectures dedicated to recursive convolutional encoders. The principle is based on the optimization of blocks that calculate the remainder of the polynomial division which constitute the critical operation of the encoding. This approach is generalized to recursive IIR filters. The main architectural characteristics being aimed are high flexibility and scalability, yet preserving a good trade-off between the amount of resources used (and hence, area consumption) and the obtained performance (operation speed). The second topic concerns the developing of a methodology for designing FS (fault-secure) encoders, improving the tolerance of digital integrated circuits. The proposed approach consists in adding an extra blocks to the encoders, allowing online error detection. The proposed solutions offer a good compromise between complexity and frequency operation. For even higher throughput, parallel-pipelined implementations of FS encoders were considered. Different fault injection campaigns of single, double, and random errors were applied to the encoders in order to evaluate error detection rates. The study of dependable architecture was extended to pipeline-parallel decoders for cyclic block codes. This approach is based on a slight modification of the parallel-pipeline architectures developed at LICM laboratory, introducing some redundancy in order to make it dependable

<p>The complex work of designing new ASICs today and the increasing costs of time to market (TTM) delays are putting high responsibility on the research and development teams to make fault free designs. The main purpose of implementing a static rule checking tool in the design flow today is to find errors and bugs in the hardware definition language (HDL) code as fast and soon as possible. The sooner you find a bug in the design, the shorter the turnaround time becomes, and thereby both time and money will be saved.</p><p>There are a couple of tools in the market that performs static HDL analysis and they vary in both price and functionality. In this project mainly Atrenta Spyglass was evaluated but similar tools were also evaluated for comparison purpose.</p><p>The purpose of this master thesis was to evaluate the need of implementing a rule checking tool in the design flow at the Digital ASIC department PDU Base Station development in Kista, who also was the commissioner for this project. Based on the findings in this project it is recommended that a static rule checking tool is introduced in the design flow at the ASIC department. However, in order to determine which of the different tools the following pointers should be regarded:</p><p>• If the tool is only going to be used as for lint checks (elementary structure and code checks) on RTL, then the implementation of Mentors Design Checker is advised.</p><p>• If the tool is going to be used for more sophisticated structural checks, clock tree/reset tree propagation, code checks, basic constraints checks, basic Clock Domain Crossings (CDC) checks, then Synopsys LEDA is advised.</p><p>• If the tool is going to be used as for advanced structural checks, extensive clock tree/reset tree propagation, code checks, constraints checks, functional Design For Test (DFT) checks (as testmode signal propagation) and functional CDC checks on RTL as well as on netlist level, then Atrenta Spyglass is advised.</p><p>The areas regarding checks that could be of interest for Ericsson is believed to be regular lint checks for RTL (naming, code and basic structure), clock/reset tree propagation (netlist and RTL), constraints and functional DFT checks (netlist and RTL).</p>

<p>Micro processors built specifically for digital signal processing are DSP processors. DSP is one of the core technologies in rapidly growing applications like communications and audio processing. The estimated growth of DSP processors in the last 6 years is over 40%. The variety of DSP capable processors for various applications also increased with the rising popularity of DSP processors. The design flow and architecture of such processors are not commonly available to students for learning.</p><p>This report is a structured approach to design and implementation of an embedded DSP processor core for voice, audio and video codec. The report focuses on the design requirement specification, senior instruction set and assembly manual release, micro architecture design and implementation of the core. Details about the core verification are also included in this report. The instruction set of this processor supports running basic kernels of BDTI benchmarking.</p>

The widespread use of microprocessor chips in high performance applications like graphics simulators and low power applications like mobile phones, laptops, medical applications etc. has made power estimation an important step in the manufacture of VLSI chips. It has become necessary to estimate the power consumption not only after the circuits have been laid out, but also during the design of the modules of the microprocessor at higher levels of design abstraction. The design of a microprocessor is complex and is performed at multiple layers of abstraction before it finally gets manufactured. The processor is first conceptually designed using blocks at the system level, and then modeled using a high-level language (C, C++, SystemC). This enables the early development of software applications using these high-level models. The C/C++ model is then translated to a hardware description language (HDL), that typically corresponds to the register transfer level (RT-Level). Once the processor is defined at the RT-Level, it is synthesized into gates and state elements based on user-defined constraints. In this thesis, novel techniques to estimate the power consumed by the microprocessor circuits at the gate level and RT-level of abstraction are presented. At the gate level, the average power consumed by microprocessor circuits is straight-forward to estimate, as the implementation is known. However, estimating the maximum or peak instantaneous power consumed by the microprocessor as a whole, when it is executing instructions, is a hard problem due to the high complexity of the state space involved. An hierarchical approach to estimate the peak power using powerful search techniques and formal tools is presented in this thesis. This approach has been extended and applied to solve the problem of estimating the maximum supply drop. Details on this extension and a discussion of promising results are also presented. In addition, this approach has been applied to explore the possibility of minimizing the leakage component of power dissipation, when the processor is idle. At the register transfer level, estimating the average power consumed by the circuits of the microprocessor is by itself a challenging problem. This is due to the fact that their implementation is unknown at this level of abstraction. The average power consumption directly depends on the implementation. The implementation, in turn, depends on the performance constraint imposed on the microprocessor. One of the factors affecting the performance of the microprocessor, is the speed of operation of its circuits. Considering these factors and dependencies (for making early design decisions at the RT-Level), a methodology that estimates the power vs. delay curves of microprocessor circuits has been developed. This will enable designers to make design decisions for even rudimentary designs without going through the time consuming process of synthesis. / text

The complex work of designing new ASICs today and the increasing costs of time to market (TTM) delays are putting high responsibility on the research and development teams to make fault free designs. The main purpose of implementing a static rule checking tool in the design flow today is to find errors and bugs in the hardware definition language (HDL) code as fast and soon as possible. The sooner you find a bug in the design, the shorter the turnaround time becomes, and thereby both time and money will be saved. There are a couple of tools in the market that performs static HDL analysis and they vary in both price and functionality. In this project mainly Atrenta Spyglass was evaluated but similar tools were also evaluated for comparison purpose. The purpose of this master thesis was to evaluate the need of implementing a rule checking tool in the design flow at the Digital ASIC department PDU Base Station development in Kista, who also was the commissioner for this project. Based on the findings in this project it is recommended that a static rule checking tool is introduced in the design flow at the ASIC department. However, in order to determine which of the different tools the following pointers should be regarded: • If the tool is only going to be used as for lint checks (elementary structure and code checks) on RTL, then the implementation of Mentors Design Checker is advised. • If the tool is going to be used for more sophisticated structural checks, clock tree/reset tree propagation, code checks, basic constraints checks, basic Clock Domain Crossings (CDC) checks, then Synopsys LEDA is advised. • If the tool is going to be used as for advanced structural checks, extensive clock tree/reset tree propagation, code checks, constraints checks, functional Design For Test (DFT) checks (as testmode signal propagation) and functional CDC checks on RTL as well as on netlist level, then Atrenta Spyglass is advised. The areas regarding checks that could be of interest for Ericsson is believed to be regular lint checks for RTL (naming, code and basic structure), clock/reset tree propagation (netlist and RTL), constraints and functional DFT checks (netlist and RTL).

abstract: Digital systems are increasingly pervading in the everyday lives of humans. The security of these systems is a concern due to the sensitive data stored in them. The physically unclonable function (PUF) implemented on hardware provides a way to protect these systems. Static random-access memories (SRAMs) are designed and used as a strong PUF to generate random numbers unique to the manufactured integrated circuit (IC). Digital systems are important to the technological improvements in space exploration. Space exploration requires radiation hardened microprocessors which minimize the functional disruptions in the presence of radiation. The design highly efficient radiation-hardened microprocessor for enabling spacecraft (HERMES) is a radiation-hardened microprocessor with performance comparable to the commercially available designs. These designs are manufactured using a foundry complementary metal-oxide semiconductor (CMOS) 55-nm triple-well process. This thesis presents the post silicon validation results of the HERMES and the PUF mode of SRAM across process corners. Chapter 1 gives an overview of the blocks implemented on the test chip 25. It also talks about the pre-silicon functional verification methodology used for the test chip. Chapter 2 discusses about the post silicon testing setup of test chip 25 and the validation of the setup. Chapter 3 describes the architecture and the test bench of the HERMES along with its testing results. Chapter 4 discusses the test bench and the perl scripts used to test the SRAM along with its testing results. Chapter 5 gives a summary of the post-silicon validation results of the HERMES and the PUF mode of SRAM. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017