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Design and Implementation of an Efficient SCA Framework for Software-Defined RadiosAguayo Gonzalez, Carlos R. 02 October 2006 (has links)
Software Defined Radio (SDR) is a relatively new approach to develop wireless communication systems. SDR presents a framework for developing flexible, reconfigurable devices intended to alleviate some of the issues arising from the evolution of wireless technology. The Software Communications Architecture (SCA), developed by the Joint Tactical Radio System program of the US Department of Defense, is an open architecture for implementing SDR, relying on commercial technology, standard interfaces, and well-known design patterns. Although the SCA is intended to provide easier, faster development of flexible applications that are upgradeable and maintainable, the acceptance of the architecture has been limited in part by traditional radio engineers' lack of understanding modern software engineering techniques. Because of the steep learning curve, some developers face frustration and serious delays when first introduced to the SCA. This work presents a comprehensive tutorial which introduces radio engineers to the SCA and the techniques used in it.
Another concern for accepting the SCA are the performance, size, cost, and power consuption difficulties faced in early implementations of the architecture. Traditionally, SCA implementations have been developed for platforms based on General Purpose Processors. This approach, while believed to be the easiest to implement, does not make the best out of available processor technology. In order to provide a more efficient implementation of radios based on the SCA, we present the design and development of an SCA Core Framework version 2.2 for a homogeneous TI C64 DSP platform. This framework is implemented by leveraging the existing implementation of the Open-Source SCA Implementation::Embedded (OSSIE) by porting it to the C64 platform. Two sample waveforms are developed and deployed to demonstrate the functionality of the framework. Preliminary performance and memory footprint profiling results are provided. / Master of Science
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