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1	A Method for Skew-free Distribution of Digital Signals Using Matched Variable Delay Lines Knight, Thomas, Wu, Henry M. 01 March 1992 (has links) The ability to distribute signals everywhere in a circuit with controlled and known delays is essential in large, high-speed digital systems. We present a technique by which a signal driver can adjust the arrival time of the signal at the end of the wire using a pair of matched variable delay lines. We show an implemention of this idea requiring no extra wiring, and how it can be extended to distribute signals skew-free to receivers along the signal run. We demonstrate how this scheme fits into the boundary scan logic of a VLSI chip. clock distribution synchronization skew compensation sphase adjustment
2	Modeling and Analysis of High-Frequency Microprocessor Clocking Networks Saint-Laurent, Martin 19 July 2005 (has links) Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems. Phase-locked loops Interlevel coupling noise Power-performance tradeoff Skew compensation Interconnect Power supply noise Skew Clock distribution Low-power design Jitter MOSFET model Timing circuits Design and construction Phase-locked loops

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A Method for Skew-free Distribution of Digital Signals Using Matched Variable Delay Lines

Modeling and Analysis of High-Frequency Microprocessor Clocking Networks