CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior / This work presents a comparative evaluation of three single-phase neutral point clamped multilevel inverters, based on switching cells, which have as a common characteristic the capacity increase of the total output current of the converters without increasing the current efforts in semiconductors. The technique employed to perform this evaluation consists primarily on individual analysis of the classical three level topology, applying only the parallelism of switching cells. Then a detailed analysis of the main topology evaluated in this work is performed. It is the five level neutral point clamped inverter, based on multi-state switching cell, which uses multilevel interleaved converters, coupled magnetically through an autotransformer in order to distribute uniformly the total output current between their windings, and consequently between the semiconductors of the converter. In addition to presenting reduced conduction losses in the semiconductors, this technique also provides a reduction in volume and weight of magnetic components due to frequency of operation of reactive elements is a multiple of the switching frequency of the switches. Consequently, the resulting converters present high efficiency, high power density and low harmonic distortion for the output voltage and output current. The theoretical analysis of the five level neutral point clamped inverter, based on multi-state switching cell, is verified by digital simulation and by 5 kW prototypes experimentation. Simulation and experimental results are also presented for the third topology analyzed, the five level neutral point clamped inverter, based on interleaved switching cells. Finally, a comparative evaluation is performed for the three inverters analyzed. / Este trabalho apresenta a avaliaÃÃo comparativa de trÃs inversores multinÃveis monofÃsicos com grampeamento do ponto central, baseados em cÃlulas de comutaÃÃo, que apresentam como caracterÃstica comum a elevaÃÃo da capacidade da corrente total de saÃda dos conversores sem aumentar os esforÃos de corrente nos semicondutores. A tÃcnica utilizada para realizar esta avaliaÃÃo consiste, primeiramente, na anÃlise individual da topologia clÃssica de trÃs nÃveis, aplicando apenas o paralelismo de cÃlulas de comutaÃÃo. Em seguida à realizada a anÃlise detalhada da principal topologia avaliada neste trabalho. Trata-se do inversor de cinco nÃveis com grampeamento do ponto central, baseado na cÃlula de comutaÃÃo de mÃltiplos estados, que utiliza conversores multinÃveis intercalados, acoplados magneticamente atravÃs de um autotransformador que, por sua vez, tem como finalidade distribuir uniformemente a corrente total de saÃda entre os enrolamentos e, consequentemente, entre os semicondutores do conversor. AlÃm de apresentar perdas de conduÃÃo reduzidas nos semicondutores, este conversor tambÃm apresenta uma reduÃÃo no volume e peso dos componentes magnÃticos, devido à frequÃncia de operaÃÃo dos elementos passivos possuir um valor mÃltiplo da frequÃncia de comutaÃÃo dos interruptores. Como consequÃncia, os conversores resultantes apresentam alto rendimento, alta densidade de potÃncia e uma baixa distorÃÃo harmÃnica total para a tensÃo e corrente de saÃda. A anÃlise teÃrica do inversor de cinco nÃveis com grampeamento do ponto central, baseado na cÃlula de comutaÃÃo de mÃltiplos estados, à verificada atravÃs de simulaÃÃo computacional e da experimentaÃÃo obtida a partir de protÃtipos desenvolvidos para uma potÃncia de 5 kW. SÃo tambÃm apresentados resultados de simulaÃÃo e experimentais para a terceira topologia analisada, o inversor de cinco nÃveis com grampeamento do ponto central, baseado em cÃlulas de comutaÃÃo intercaladas. Finalmente, à realizada uma avaliaÃÃo comparativa entre os trÃs inversores analisados.

Parasitic inductance in power modules generates voltage spikes and current ringing during switching which cause extra stress in power electronic devices, increase electromagnetic interference (EMI), and degrade the performance of the power converter system. As newer power devices have faster switching speeds and higher power ratings, the effect of the parasitic inductance of the power module is more pronounced. This dissertation proposes a novel packaging method for power electronics modules based on the concepts of novel switching cells: P-cell and N-cell. It can reduce the stray inductance in the current commutation path in a phase-leg module and hence improve the switching behavior. Taking an insulated gate bipolar transistor (IGBT) as an example, two phase-leg modules, specifically a conventional module and a P-cell and N-cell based module were designed. Using Ansoft Q3D Extractor, electromagnetic simulation was carried out to extract the stray inductance from the two modules. An ABB 1200 V / 75 A IGBT model and a diode model were built for simulation study. Circuit parasitics were extracted and modeled. Switching behavior with different package parasitics was studied based on the Saber simulation. Two prototype phase-leg modules were fabricated. The parasitics were measured using a precision impedance analyzer. The measurement results agree with the simulation very well. A double pulse tester was built in laboratory. Several approaches were used to reduce the circuit and measuring parasitics. From the switching characteristics of the two modules, it was verified that the larger stray inductance in the layout causes higher voltage overshoot during turn off, which in turn increases the turn off losses. Multichip (two in parallel) IGBT modules applying novel switching cells was also designed. The parasitics were extracted and compared to a conventional design. The overall loop inductance was reduced in the proposed module. However, the mismatch of the paralleled branches was larger.