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The increasingly more sophisticated systems that are nowadays implemented on a single chip are placing stringent requirements on the test industry. New test strategies, equipment, and methodologies need to be developed to sustain the constant increase in demand for consumer and communication electronics. Techniques for built-in-self-test (BIST) and design-for-test (DFT) strategies have been proven to offer more feasible and economical testing solutions. / Previous works have been conducted to perform on-chip testing, characterization, and measurement of signals and components. The current thesis advances those techniques on many levels. In terms of performance, an increase of more than an order of magnitude in speed is achieved. 70-GHz (effective sampling) on-chip oscilloscope is reported, compared to 4-GHz and 10-GHz ones in previous state-of-the-art implementations. Power dissipation is another area where the proposed work offer a superior solution compared to previous alternatives. All the proposed circuits do not exceed a few milliWatts of power dissipation, while performing multi-GHz high-speed signal capture at a medium resolution. Finally, and possibly most importantly, all the proposed circuits for test rely on a different form of signal processing; the time-based approach. It is believed that this approach paves the path to a lot of new techniques and circuit design skills that can be investigated more deeply. As an integral part of the time-based processing approach for GHz signal capture, this thesis verifies the advantages of using time amplification. The use of such amplification in the time domain is materialized with experimental results from three specific integrated circuits achieving different tasks in GHz high-speed in-situ signal measurement and characterization. Advantages of using such time-based approach techniques, when combined with the use of a front-end time amplifier, include noise immunity, the use of synthesizable digital cells, and circuit building blocks that track the technology scaling in terms of area and speed.

FFT-based tests (e.g. gain, distortion, SNR, etc.) from a device-under-test (DUT) exhibit normal distributions when the measurement is repeated many times. Hence, a statistical approach to evaluate the accuracy of these measurements is traditionally applied. The noise in a DSP-based mixed-signal test system severely limits its measurement accuracy. Moreover, in high-speed sampled-channel applications the jitter-induced noise from the DUT and test equipment can severely impede accurate measurements. / A new digitizer architecture and post-processing methodology is proposed to increase the measurement accuracy of the DUT and the test equipment. An optimal digitizer design is presented which removes any measurement bias due to noise and greatly improves measurement repeatability. Most importantly, the presented system improves accuracy in the same test time as any conventional test. / An integrated mixed-signal test core was implemented in TSMC's 0.18 mum mixed-signal process. Experimental results obtained from the mixed-signal integrated test core validate the proposed digitizer architecture and post processing technique. Bias errors were successfully removed and measurement variance was improved by a factor of 5.

Thesis(M.S.)--Auburn University, 2004. / Abstract. Vita. Includes bibliographic references (p.123-125).

Thesis (Ph. D.)--University of Washington, 2005. / Vita. Includes bibliographical references (p. 121-130).

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 97-102).

Library characterization and 'Static Timing Analysis' (STA) are widely used in the design of modern CMOS integrated circuits to confirm that critical timing constraints are met. While many commercial tools are available to do timing validation using library characterization and static timing analysis, their operation depends on calculations relative to a global synchronous clock. This thesis applies timing validation to circuits from which the global synchronous clock is absent, making application of commercial tools difficult. Previous work at the University of Southern California (USC) showed how to overcome the incompatibility of commercial STA tools for asynchronous circuits. This thesis shows how to overcome the incompatibility of library characterization with respect to asynchronous circuits, and ties the results into the STA solution of USC. The particular family of circuits considered in this thesis is called GasP. GasP circuits are light in area and light in power. They have demonstrated operation at about twice the throughput one would expect from conventional clocked circuits. This makes GasP circuits excellent candidates for modern many-core, concurrent network-on-chip and system-on-chip architectures. In part, GasP circuits achieve their performance advantages by using a `single-track' signaling protocol. Two GasP modules communicate with each other over a single wire. One module drives the wire up and a second module at the other end of the wire drives the wire down. This conflicts with the common assumption that wires are driven only from one end. As a result, special circuitry is needed to characterize a GasP library module. This thesis shows how to break a GasP module and its timing constraints into manageable pieces and how to simulate and collect the data relevant for characterization and static timing analysis. When combined with software tools for identifying the critical timing constraints, the results of this work will provide confidence in the correct operation of GasP circuits.

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System-on-chips (SoCs) have become fundamental components in modern electronic devices, from low-power microcontrollers to high-performance AI computing systems. With the increasing demand for performance and efficiency, innovative approaches in power management and clocking mechanisms are increasingly important. One such approach combines multiple regulator architectures to form a hybrid voltage regulation, which this work demonstrated with buck converters and digital low-dropout (D-LDO) regulators. Additionally, the increasing demand for sub-micro-second voltage scaling in SoCs has pushed regulators to be fully integrated in-package and/or on-chip. Buck converters still offer the highest efficiency compared to other converter topologies but present integration challenges that this work addresses by utilizing a package integrated voltage regulator (PIVR) with full back-end integration of magnetic-core power inductors. The on-chip D-LDO demonstrated a fully standard cell-based distributed design integrated into an advanced 12nm FinFET process. A focus on reducing excess timing margins has led to a push towards advanced clocking mechanisms like adaptive clocking, which has caused a shift from more traditional PLL-based dynamic voltage and frequency scaling to unified voltage and frequency scaling architectures that use tunable replica oscillators to decrease timing excess timing margins due to voltage droop, process variations, thermals, and aging. This work implemented UVFS with an HVR architecture using a multi-output PIVR cascaded with on-chip D-LDOs and demonstrated it in a complex 22-core network-on-chip SoC in 12nm FinFET.