Snehal Udar, for the Doctor of Philosophy degree in Electrical and Computer Engineering, presented on May 4, of 2011, at Southern Illinois University Carbondale. TITLE: BUILT-IN SCHEMES FOR TEST PATTERN GENERATION AND FAULT LOCATION MAJOR PROFESSOR: Dr. D. Kagaris In this dissertation, we studied the areas of test pattern generation and fault location for detecting and diagnosing the faults in today's complex chips. In the first problem, a novel reseeding based test pattern generation scheme is analyzed by proposing a hardware efficient technique that uses irreducible polynomial-primitive element pair to generate distinct subsequences of test patterns. It is shown that for the given characteristic polynomial the hardware cost remains the same irrespective of the number of seeds required to generate the test sequence of given length. This scheme is targeted at generating pseudo-random test patterns that detect easy-to-detect faults. A counter based reseeding scheme is further analyzed that embeds a given set of fully specified test patterns in minimum number of clock cycles. Second problem investigates the effectiveness of inserting observation points on the circuit lines that along with primary output lines distinguish a given set of faults. Three hardware based approaches are proposed that aim at inserting minimum observation points, and are compared with each other for different diagnostic resolutions.

Thesis(M.S.)--Auburn University, 2006. / Abstract. Vita. Includes bibliographic references (p.74-78).

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This thesis presents four different techniques for improving the average-case performance of deterministic sequential circuit Automatic Test Patterns Generators (ATPG). Three techniques make use of information gathered during test generation to help identify more unjustifiable states with higher percentage of "don't care" value. An approach for reducing the search space of the ATPG was introduced. The technique can significantly reduce the size of the search space but cannot ensure the completeness of the search. Results on ISCAS–85 benchmark circuits show that all of the proposed techniques allow for better fault detection in shorter amounts of time. These techniques, when used together, produced test vectors with high fault coverages. Also investigated in this thesis is the Decision Inversion Problem which threatens the completeness of ATPG tools such as HITEC or ATOMS. We propose a technique which can eliminate this problem by forcing the ATPG to consider search space with certain flip-flops untouched. Results show that our technique eliminated the decision inversion problem, ensuring the soundness of the search algorithm under the 9-valued logic model. / Master of Science

Dėl didėjančio integrinių schemų sudėtingumo ir darbinių dažnių vėlinimo gedimų nustatymas tampa svarbia schemų kūrimo dalimi. Programiniai schemų prototipai leidžia atlikti schemų testavimą ankstyvojoje stadijoje. Šiame darbe yra pateikiama vėlinimo gedimų nustatymo metodų analizė ir jų palyginimas. Tyrimo objektu pasirinktas perėjimo gedimų modelis. Dokumente aprašomas AntiRandom metodo pritaikymo galimybės funkcinių testų generavimui. Taip pat yra trumpai apžvelgiami egzistuojantys sprendimai rinkoje. Projektavimo skyriuje yra aprašoma suprojektuota ir realizuota sistema, kuri susideda iš dviejų posistemių: funkcinių testų generatoriaus bei rezultatų kaupimo ir analizės posistemės. Funkcinių testų generatoriuje realizuoti du atsitiktinio ir AntiRandom metodai. Paskutinėje dokumento dalyje yra pateiktas atliktas eksperimentinis tyrimas su realizuota sistema. Taip pat yra pateikiami eksperimentinio tyrimo metu pasiekti rezultatai bei padarytos viso darbo išvados. / The increasing complexity of integrated circuits and operating frequency led delay fault identification to become an important part of the schemes development. Software prototypes allow to start testing phase at an early stage. This work covers the delay fault detection method analysis and comparison. For the study is selected transition fault identification. The paper describes the AntiRandom method and customization possibilities for the functional test generation. There is also a brief overview of an existing solutions on the market. The design section describes the designed and implemented system which consists of two subsystems: functional tests generator and results storage and analysis subsystem. Functional test generator has two random methods and customized AntiRandom method. The last part of the document covers an experimental study for the created system. It consists of results of the experiments and conclusions of the whole work.

Capacitive crosstalk between adjacent signal wires in integrated circuits may lead to noise or a speedup or slowdown in signal transitions. These in turn may lead to circuit failure or reduced operating speed. This thesis focuses on generating test patterns to induce crosstalk-induced signal delays, in order to determine whether the circuit can still meet its timing specification. A timing-driven test generator is developed to sensitize multiple aligned aggressors coupled to a delay-sensitive victim path to detect the combination of a delay spot defect and crosstalk-induced slowdown. The framework uses parasitic capacitance information, timing windows and crosstalk-induced delay estimates to screen out unaligned or ineffective aggressors coupled to a victim path, speeding up crosstalk pattern generation. In order to induce maximum crosstalk slowdown along a path, aggressors are prioritized based on their potential delay increase and timing alignment. The test generation engine introduces the concept of alignment-driven path sensitization to generate paths from inputs to coupled aggressor nets that meet timing alignment and direction requirements. By using path delay information obtained from circuit preprocessing, preferred paths can be chosen during aggressor path propagation processes. As the test generator sensitizes aggressors in the presence of victim path necessary assignments, the search space is effectively reduced for aggressor path generation. This helps in reducing the test generation time for aligned aggressors. In addition, two new crosstalk-driven dynamic test compaction algorithms are developed to control the increase in test pattern count. The proposed test generation algorithm is applied to ISCAS85 and ISCAS89 benchmark circuits. SPICE simulation results demonstrate the ability of the alignment-driven test generator to increase crosstalk-induced delays along victim paths.

In this paper a test set embedding based on accumulator driven by an odd additive constant is presented. The problem is formulated around finding the location of the test pattern in the sequence generated by the accumulator, given a odd constant C and test set T, in terms of linear Diophantine equation of two variables. We show that the search space for finding the best constant corresponding to the shortest length, is greatly reduced. Experimental results show a significant improvement in run time with practically acceptable test length.

No description available.

Test and Diagnosis are critical areas in semiconductor manufacturing. Every chip manufactured using a new or premature technology or process needs to be tested for manufacturing defects to ensure defective chips are not sold to the customer. Conventionally, test is done by mounting the chip on an Automated Test Equipment (ATE) and applying test patterns to test for different faults. With shrinking feature sizes, the complexity of the circuits on chip is increasing, which in turn increases the number of test patterns needed to test the chip comprehensively. This increases the test application time which further increases the cost of test, ultimately leading to increase in the cost per device. Furthermore, chips that fail during test need to be diagnosed to determine the cause of the failure so that the manufacturing process can be improved to increase the yield. With increase in the size and complexity of the circuits, diagnosis is becoming an even more challenging and time consuming process. Fast diagnosis of failing chips can help in reducing the ramp-up to the high volume manufacturing stage and thus reduce the time to market. To reduce the time needed for diagnosis, efficient diagnostic patterns have to be generated that can distinguish between several faults. However, in order to reduce the test application time, the total number of patterns should be minimized. We propose a technique for generating diagnostic patterns that are inherently compact. Experimental results show up to 73% reduction in the number of diagnostic patterns needed to distinguish all faults. Logic Built-in Self-Test (LBIST) is an alternative methodology for testing, wherein all components needed to test the chip are on the chip itself. This eliminates the need of expensive ATEs and allows for at-speed testing of chips. However, there is hardware overhead incurred in storing deterministic test patterns on chip and failing chips are hard to diagnose in this LBIST architecture due to limited observability. We propose a technique to reduce the number of patterns needed to be stored on chip and thus reduce the hardware overhead. We also propose a new LBIST architecture which increases the diagnosability in LBIST with a minimal hardware overhead. These two techniques overcome the disadvantages of LBIST and can make LBIST more popular solution for testing of chips. Modern designs may contain a large number of small embedded memories. Memory Built-in Self-Test (MBIST) is the conventional technique of testing memories, but it incurs hardware overhead. Using MBIST for small embedded memories is impractical as the hardware overhead would be significantly high. Test generation for such circuits is difficult because the fault effect needs to be propagated through the memory. We propose a new technique for testing of circuits with embedded memories. By using SMT solver, we model memory at a high level of abstraction using theory of array, while keeping the surrounding logic at gate level. This effectively converts the test generation problem into a combinational test generation problem and make test generation easier than the conventional techniques. / Ph. D.

Automatinis testų rinkinių generavimas (pasaulyje priimtas angliškas sutrumpinimas – ATPG) yra pakankamai senai sprendžiama problema. Jos tikslas – surasti optimalų testinių vektorių sekas, kurios pilnai užtikrintų visas schemos gamybos etape padarytas klaidas per mažiausią laiką. Vienas iš skaitmeninių schemų testavimo ir testų rinkinių sudarymo metodas yra funkcinis testavimo metodas. Jo privalumai yra tame, kad testų rinkinių sudarymo programa nežino schemos vidinės struktūros, o testuoja tik idealų schemos modelį, kuri yra pateikta juodos dėžės pavidale, tai yra programa gali gauti idealaus schemos reakciją į tam tikrą įvedimo signalų vektorių. Šiame darbe parinktas funkcinis testavimo metodas. Šiame darbe aprašoma testinių rinkinių atrinkimo programinės įrangos teorinė bazė, automatinio testų rinkinio formavimo trumpa istorinė apžvalga, baltos ir juodos dėžės modelių pagristų formavimo algoritmų palyginimai. Aprašoma programų sistemos statinė struktūra bei jos komponentai, sistemos panaudojimo atvejai. Tyrimų dalyje aprašoma tyrimo metodika, siūlomi programos kokybės tobulinimo metodai. Eksperimentų dalyje aprašomi tyrimų eksperimentų rezultatai. / Automated test pattern generation (ATPG) problem is being solved for a relatively long time. Its' point is to find optimal test vector sequences, which would cover most of all production-caused digital circuit faults and would run for the minimum amount of time. One of the ways to test and generate test vectors for digital circuits is functional test method. Its' benefit is that system does not need to be aware of digital circuit's inner logical model, but has to deal only with the input, so that just the ideal model of the digital circuit can be used as a "black box". The program's algorithm can get ideal digital circuit's reaction for corresponding input test vector. This paper will mostly cover functional model approach to ATPG. This paper covers automated test vector generation software basic theory with brief historical review, comparison of white box and black box models' testing and test vector generation algorithms. Also the software's static structures along with its components, system’s typical use cases are covered. The research part of the paper is focused mostly on the algorithms used, containing research methods which provide the results for the experiment part.